Oversize Store to Load Forwarding via Gather Buffer

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Solution Overview

Problem

Modern processors face inefficiencies and latency due to the complexity of handling out-of-order instruction execution, particularly when processing oversize store and load operations, which can exceed the data field width of store and load queues, leading to challenges in data handling and processing.

Innovation Solution

The processor employs a Load Store Execution Unit (LSU) with a store queue and a gather buffer to process oversize data by executing two passes through the LSU, where the first pass stores one portion of the data in the gather buffer and the second pass merges it with the remaining portion from the store queue, allowing oversize data to be stored in multiple entries and efficiently handled.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the store queue data field width is increased to accommodate oversize data, then the processor can handle oversize store and load operations directly, but the hardware cost and complexity increase

Engineering Contradiction:
Improveability to handle oversize dataVSAvoidstore queue entry size
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides oversize data into multiple portions and stores them in separate store queue entries. Each entry contains only the necessary portion of the data, allowing the store queue to handle oversize operations without requiring each entry to accommodate the full oversize width. This segmentation resolves the contradiction by maintaining entry-size efficiency while achieving oversize data handling capability through multiple coordinated entries.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the processor executes instructions in-order, then the handling of store and load operations is simpler, but processing efficiency and throughput decrease

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidinstruction handling complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a gather buffer as an intermediary structure between the store queue and the load operation. When handling oversize load operations, the gather buffer temporarily holds portions of data retrieved from multiple store queue entries, coordinating the complex in-order retrieval process. This intermediary simplifies the overall handling complexity by providing a dedicated buffer management layer that manages the in-order execution requirements without burdening the entire processor architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If the store queue entries are sized for oversize data, then oversize operations can be processed directly, but the processor latency increases due to the complexity of managing larger data fields

Engineering Contradiction:
Improveoversize data processing capabilityVSAvoidprocessor latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

By segmenting oversize data into smaller portions stored in individual queue entries, the processor can retrieve and process these portions in parallel or in an optimized sequence through the gather buffer. This segmentation reduces the time required to manage and process oversize data compared to using a single large entry, as the smaller segments can be handled more efficiently through the pipelined architecture.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11379241B2Handling oversize store to load forwarding in a processor
Publication Date: 2022.07.05 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US11379241B2 patent drawing
  • US11379241B2 patent drawing
  • US11379241B2 patent drawing

AI summary

System includes at least one computer processor having a load store execution unit (LSU) for processing load and store instructions, wherein the LSU includes (a) a store queue having a plurality of entries for storing data, each store queue entry having a data field for storing the data, the data field having a width for storing the data; and (b) a gather buffer for holding data, wherein the processor is configured to: process oversize data larger than the width of the data field of the store queue, and process an oversize load instruction for oversize data by executing two passes through the LSU, a first pass through the LSU configured to store a first portion of the oversize data in the gather buffer and a second pass through the LSU configured to merge the first portion of the oversize data with a second portion of the oversize data.