Oversized TSV Stop Layer for Protecting Thin Interconnects
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Solution Overview
Problem
The etching process used to form through-substrate vias (TSVs) in integrated chip fabrication can damage thin interconnect layers, leading to reliability issues such as time-dependent dielectric breakdown, leakage, and chip failure due to over-etching.
Innovation Solution
Incorporating an oversized via that acts as a stop layer during the etching process, which is larger than standard vias and extends past the opposing sides of the TSV, effectively mitigating over-etching by forming a thick interconnect structure with the second interconnect wire, thereby preventing damage to the thin interconnect layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an etching process is used to form through-substrate vias (TSVs), then TSV formation is achieved, but thin interconnect layers are damaged leading to reliability issues
Solution Approach 1:
An oversized via structure is introduced as an intermediary protective element between the etching process and the thin interconnect layers. This oversized via acts as a sacrificial stop layer that absorbs the over-etching damage, preventing the etchant from reaching and damaging the thin interconnect layers below. The oversized via is formed with a larger cross-sectional area than standard vias, providing sufficient material bulk to serve as an effective etch stop.
2Reliability
If oversized via is used to prevent over-etching, then interconnect layer protection is improved, but device complexity increases
Solution Approach 1:
The oversized via structure serves multiple functions simultaneously: it acts as an etch stop layer to protect thin interconnect layers from over-etching damage, provides an enlarged contact area for improved electrical connection, and can serve as a reinforcement structure for TSV mechanical stability. By combining multiple functions into a single structural element, the need for separate protective layers is eliminated, thereby reducing overall device complexity despite the enlarged via dimensions.
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed on a first side of a substrate. A second via is disposed on the first side of the substrate and is laterally separated from the first via. An interconnect wire vertically contacts the second via. A through-substrate via (TSV) extends through the substrate to physically contact one or more of the second via and the interconnect wire. The first via has a first width and the second via has a second width. The second width is between approximately 2,000% and approximately 5,000% larger than the first width.