Oversized TSV Stop Via to Prevent Interconnect Over-Etching
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Solution Overview
Problem
During the integrated chip fabrication process, the etching process used to form through-substrate vias (TSVs) can damage thin interconnect layers, leading to reliability issues such as time-dependent dielectric breakdown, leakage, and chip failure due to over-etching.
Innovation Solution
Incorporating an oversized via that acts as a stop layer for the TSV etching process, which is larger than standard vias and extends laterally past the TSV, thereby preventing over-etching and protecting the thin interconnect layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an etching process is used to form through-substrate vias (TSVs), then TSV formation is achieved, but the thin interconnect layers are damaged leading to reliability issues
Solution Approach 1:
An oversized via structure is introduced as an intermediary protective element between the etching process and the thin interconnect layers. This oversized via acts as a sacrificial stop layer that absorbs the over-etching damage, preventing direct contact between the harmful etchant and the sensitive interconnect layers, thus resolving the contradiction between achieving precise TSV formation and maintaining chip reliability
Solution Approach 2:
The oversized via is formed in advance before the TSV etching process, creating a protective cushion or buffer zone. This pre-formed structure extends laterally past the TSV opening and provides a protective barrier that absorbs the mechanical and chemical stress of the etching process, preventing damage to the underlying interconnect layers before the etching even occurs
2Productivity
If the etching process extends beyond the intended depth, then complete TSV formation is achieved, but over-etching damages the dielectric structure
Solution Approach 1:
The oversized via serves as a mediator that decouples the etching depth control from the final TSV dimensions. The etching process can proceed aggressively through the substrate without precise depth control, as the oversized via structure absorbs the excess etching, allowing high productivity while maintaining manufacturing precision through the protective intermediary
Solution Approach 2:
The potential harm of over-etching is converted into a benefit by deliberately designing an oversized via that extends laterally past the TSV opening. The over-etching that would normally be harmful is redirected to enlarge the via structure itself, transforming the manufacturing challenge into a useful feature that enhances both TSV formation efficiency and structural integrity
Data Source
AI summary
The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.