Oversized Via Design for Semiconductor Chip Stress Reduction
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Solution Overview
Problem
The structural damage to C4 interconnections in semiconductor chip packaging due to thermal stress and CTE mismatch between the chip and packaging material leads to mechanical stress and fatigue, particularly during thermal cycling and assembly processes.
Innovation Solution
The design incorporates on-chip vias and an improved ball limiting metallurgy with a thickened aluminum pad and photosensitive polyimide support to reduce stress levels, using copper/nickel metallurgy and oxide/nitride compositions to mitigate thermal expansion mismatch and enhance solder bump reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional chip packaging structures are used, then chip miniaturization and integration density are improved, but thermal stress and CTE mismatch cause mechanical stress and fatigue of C4 interconnections
Solution Approach 1:
The patent modifies the via structure parameters, specifically increasing the via diameter to create an oversized via that is at least 1.5 times the diameter of the C4 interconnection. This parameter change allows the via to accommodate thermal expansion and contraction stresses, reducing mechanical stress and fatigue on the C4 interconnections while maintaining high integration density
Solution Approach 2:
The patent employs a composite structure combining multiple materials with different properties: the oversized via is filled with conductive material (such as copper or tungsten), and the via wall is lined with barrier and adhesion layers. This composite approach creates a stress-distributing structure that mitigates CTE mismatch between the chip and packaging materials while maintaining electrical connectivity
2Ease of manufacture
If standard via designs are used, then manufacturing simplicity is maintained, but stress concentration causes physical breakage of dielectric and wiring levels
Solution Approach 1:
The patent changes the via diameter parameter to create an oversized via structure that is at least 1.5 times the C4 interconnection diameter. This design reduces stress concentration by distributing mechanical stresses over a larger area, preventing physical breakage of dielectric and wiring levels while remaining compatible with standard via fabrication processes
Solution Approach 2:
The oversized via acts as a pre-designed stress absorption zone that cushions against thermal and mechanical stresses before they can propagate to the C4 interconnections and underlying wiring. The via structure is prepared in advance to absorb and distribute stresses, preventing catastrophic failure during thermal cycling and assembly processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces relative stress levels by up to one-third compared to prior art structures, minimizing physical breakage and improving the reliability of semiconductor chip packages during thermal cycling and assembly.
Implementation Method 1
the chip and substrate ordinarily are formed from different materials having different coefficients of thermal expansion (CTE), the chip and substrate tend to expand and contract by different amounts
Implementation Method 2
The design incorporates on-chip vias and an improved ball limiting metallurgy with a thickened aluminum pad and photosensitive polyimide support to reduce stress levels
Implementation Method 3
the solder ball must be heated and softened by reflow so that it can join the chip to the solder pad on the substrate
Implementation Method 4
the solder ball must be heated and softened by reflow so that it can join the chip to the solder pad on the substrate
Data Source
AI summary
A design structure to provide a package for a semiconductor chip that minimizes the stresses and strains that arise from differential thermal expansion in chip to substrate or chip to card interconnections. An improved set of design structure vias above the final copper metallization level that mitigate shocks during semiconductor assembly and testing. Other embodiments include design structures having varying micro-mechanical support structures that further minimize stress and strain in the semiconductor package.