Over-voltage Tolerant Pass-gate Using Segmented FET Wells
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Solution Overview
Problem
MOSFET switches face issues with over/under-voltage effects leading to catastrophic failures, especially during power up and down operations, and prior art designs fail to provide adequate protection and minimize insertion loss and leakage currents across varying power supply levels.
Innovation Solution
A pass-gate switch design using parallel primary FETs with functional connection of wells to prevent pn junction forward biasing, coupled with Schottky diodes to limit forward voltage drop, ensuring proper enablement and reducing leakage currents, and employing identical circuits for enabling and power supply to maintain the off-state during power down.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two FETs are used in series to protect from over/under-voltages, then reliability is improved, but channel resistance increases
Solution Approach 1:
The pass-gate is divided into two separate FETs (first and second FETs) with different well connections. The first FET has its well connected to a first potential and the second FET has its well connected to a second potential, allowing each transistor to be optimized for specific voltage protection while maintaining low channel resistance through parallel operation during normal conditions.
Solution Approach 2:
Each FET is given different well connection characteristics - the first FET well is connected to a first potential and the second FET well is connected to a second potential. This local differentiation allows each transistor to provide specific protection functions while maintaining optimal conduction properties for their respective operating conditions.
2Object-affected harmful factors
If FETs are made larger to reduce channel resistance, then channel resistance is reduced, but chip area increases
Solution Approach 1:
The circuit dynamically switches between different FETs based on operating conditions. During normal operation, one FET provides the primary conduction path with low resistance. During over/under-voltage conditions, the other FET activates to provide protection. This dynamic operation allows using smaller transistors than would be required if both needed to operate simultaneously at full capacity.
3Reliability
If the well is connected to +V to prevent pn junction forward bias, then reliability is improved, but leakage current increases when power is turned off
Solution Approach 1:
The well connection is segmented into two separate potential systems. The first FET well is connected to a first potential and the second FET well is connected to a second potential. This segmentation allows each FET to have optimized well connections for their specific function - one optimized for normal operation with low leakage, and the other optimized for protection during power transitions.
Solution Approach 2:
The well potential parameters are changed based on operating conditions. By having the first FET well connected to a first potential and the second FET well connected to a second potential, the circuit can adjust which FET is active based on voltage conditions, thereby minimizing leakage current during power down while maintaining protection capability.
4Device complexity
If a single FET is used, then device complexity is reduced, but over/under-voltage protection is insufficient
Solution Approach 1:
Each FET is given distinct local characteristics through different well connections - the first FET has its well connected to a first potential and the second FET has its well connected to a second potential. This local quality differentiation enables each transistor to specialize in specific protection functions, achieving comprehensive over/under-voltage protection with a relatively simple two-FET structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents MOSFET failures by maintaining the off-state during power down and reducing leakage currents, ensuring reliable operation across varying power levels and increasing bandwidth while minimizing insertion loss.
Implementation Method 1
coupled with Schottky diodes to limit forward voltage drop
Data Source
AI summary
A pass-gate having a single or parallel opposite polarity FETs is disclosed. The wells of the primary transistor switches are driven from circuitry that reduces over-voltage leakage and other malfunctions. A circuit that drives the wells is also used to power enable circuits that drive the gates of the pass transistors. The use of separate circuits to the gate and the wells further reduces leakage. In the condition of power supply voltage and signal levels that are near the thresholds of the FETs involved, one or more Schottky diodes may be used across pn junctions in the FETs that will prevent turning on the pn junctions.