Ovonic Threshold Switch GeCTe Composition for Low-Leakage Memory

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Solution Overview

Problem

Current semiconductor devices face challenges in achieving miniaturization, higher speed, and reduced power consumption due to limitations in materials and structures used in memory devices, particularly in selector layers and memory cells, which affect electrical performance and reliability.

Innovation Solution

The use of a ternary GeCTe material comprising carbon, germanium, and tellurium in ovonic threshold switches, which is formed through sputtering techniques and optimized for composition and processing conditions to enhance optical bandgap, thermal stability, and endurance, is proposed to improve the performance of memory devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional materials and structures are used in memory devices, then manufacturing process is simpler, but electrical performance and reliability deteriorate

Engineering Contradiction:
Improveelectrical performance and reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs a composite structure consisting of a selector layer (e.g., GeSbTe alloy) and a memory layer (e.g., phase change material or resistive switching material) stacked together. This composite material approach enables the device to achieve superior electrical performance and reliability through the synergistic properties of different materials, while the layer-by-layer fabrication process keeps the manufacturing complexity manageable.

Inventive Principle:
Principle #40Composite materials

2Productivity

If device miniaturization is pursued, then integration density increases, but manufacturing precision requirements worsen

Engineering Contradiction:
Improveintegration densityVSAvoidlayer thickness control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent utilizes phase change material properties that undergo dramatic resistance changes at specific temperatures and compositions. By controlling deposition parameters such as sputtering power, temperature, and composition ratios during fabrication, the process achieves atomic-layer precision in thickness control, enabling miniaturization while maintaining manufacturing feasibility through parameter optimization rather than increased precision requirements.

Inventive Principle:
Principle #35Parameter changes

3Speed

If higher speed operation is implemented, then processing throughput increases, but power consumption worsens

Engineering Contradiction:
Improveprocessing speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent exploits phase transitions in the memory layer material (e.g., amorphous-to-crystalline transition) to achieve ultrafast data writing and reading operations. The phase change occurs on picosecond to nanosecond timescales, enabling high-speed operation. The transition is triggered by localized heating from laser pulses or electrical current, which confines energy consumption to only the active memory cell being written or read, rather than heating the entire device, thus achieving high speed with controlled power consumption.

Inventive Principle:
Principle #36Phase transitions

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The ternary GeCTe material demonstrates superior thermal resistance, lower leakage currents, and increased endurance, enabling better performance in memory devices and facilitating integration into non-volatile memories with reduced power consumption and improved reliability.

Implementation Method 1

The ternary GeCTe material is formed on a substrate. Forming the ternary GeCTe material includes applying a first power to a first sputtering target and applying a second power to a second sputtering target

Methodology Applied
Scientific EffectSputtering: Sputtering

Data Source

PatentUS20240373651A1Method of manufacturing semiconductor device
Publication Date: 2024.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240373651A1 patent drawing
  • US20240373651A1 patent drawing
  • US20240373651A1 patent drawing

AI summary

A semiconductor device includes a semiconductor substrate and an interconnection structure. The interconnection structure is disposed over the semiconductor substrate. The interconnection structure includes first conductive lines, second conductive lines, and ovonic threshold switches. The first conductive lines extend parallel to each other in a first direction. The second conductive lines are stacked over the first conductive lines and extend parallel to each other in a second direction perpendicular to the first direction. The ovonic threshold switches are disposed between the first conductive lines and the second conductive lines. The ovonic threshold switches include a ternary GeCTe material. The ternary GeCTe material consists substantially of carbon, germanium, and tellurium. In the ternary GeCTe material, a content of carbon is in a range from 10 to 30 atomic percent and a content of germanium is in a range from 10 to 65 atomic percent.