On-Chip Valley Search for Non-Volatile Memory Read Level Optimization
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Solution Overview
Problem
Non-volatile memory devices face challenges in error correction due to severe deterioration of memory cells, where traditional error correction codes fail to correct errors, necessitating a more effective method to extend the correction range of recovery codes.
Innovation Solution
The implementation of an on-chip valley search (OVS) operation that updates tables with detection information, allowing for a second OVS operation using a changed read level to improve error correction, and the use of a history read table to accumulate offsets for enhanced read level management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ECC circuit is used for error correction, then the correction process is simple, but it cannot correct errors when memory cell deterioration is severe
Solution Approach 1:
The patent performs an on-chip valley search (OVS) operation before the actual read operation to preliminarily determine the optimal read level. This preliminary action allows the system to adjust the read level in advance, enabling the ECC circuit to successfully correct errors that would otherwise be uncorrectable, thereby improving reliability without significantly increasing the complexity of the correction process itself.
Solution Approach 2:
The patent introduces an intermediary OVS operation between the traditional read command and the ECC correction process. This intermediary step provides detection information about memory cell states, which is then used to adjust the read level before data retrieval, serving as a bridge that enhances ECC effectiveness without directly modifying the ECC circuit itself.
2Reliability
If a read retry operation with different sensing technique is performed, then the error correction range is extended, but the search time increases
Solution Approach 1:
The OVS operation is performed as a preliminary step before the actual read operation, pre-determining the optimal read level based on detected memory cell states. This eliminates the need for time-consuming trial-and-error read retries with different sensing techniques, as the system already has the optimized read level ready, thus extending error correction range without proportionally increasing search time.
Solution Approach 2:
The system implements a feedback mechanism where the OVS operation detects the actual state of memory cells and provides this information back to adjust the read level accordingly. This feedback loop ensures that subsequent read operations use the most appropriate sensing parameters, reducing the need for repeated search operations and minimizing time loss while maximizing error correction capability.
3Measurement precision
If the read level is adjusted dynamically, then the error correction accuracy is improved, but the control complexity increases
Solution Approach 1:
The patent introduces an intermediary OVS operation that acts as a mediator between the controller and the actual read operation. This intermediary step handles the complexity of dynamic read level adjustment by performing the detection and calculation of optimal read levels separately, allowing the main read operation to simply apply the pre-calculated adjustments, thereby improving accuracy without significantly increasing overall control complexity.
Solution Approach 2:
The patent segments the read operation into two distinct phases: an OVS phase for detecting memory cell states and calculating optimal read levels, and an actual read phase for data retrieval using the pre-determined read levels. This segmentation isolates the complex control logic to a specific preliminary step, making the overall system easier to manage while achieving high error correction accuracy.
Data Source
AI summary
A storage device includes at least one non-volatile memory device and a controller configured to control the at least one non-volatile memory device. The at least one non-volatile memory device performs an on-chip valley search (OVS) operation by latching a read command at an edge of a write enable (WE) signal according to a command latch enable (CLE) signal and an address latch enable (ALE) signal. The controller receives detection information according to the OVS operation from the at least one non-volatile memory device in response to a specific command. The OVS operation includes a first OVS operation using a read level and a second OVS operation using a changed read level.