3D Integrated Circuit Oxidation Suppression Layer
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the need for expensive processing equipment to achieve finer patterns, which restricts the increase in integration density, prompting the development of three-dimensional semiconductor memory devices to overcome these limitations.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a substrate that includes a cell array region, a peripheral circuit region, and a connection region, featuring an oxidation suppressing layer and vertically stacked insulating layers and electrodes, allowing for the formation of horizontal and vertical gate insulating layers to support efficient memory cell arrangement and data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional or planar semiconductor devices are used to increase integration density, then finer patterns are required, but expensive processing equipment is needed to achieve finer patterns
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically integrated circuit devices. By stacking multiple functional circuits vertically on the substrate, the integration density is increased without requiring finer lateral patterning, thereby avoiding the need for expensive fine pattern processing equipment while achieving higher integration density.
2Manufacturing precision
If the horizontal gate insulating layer thickness varies across different regions, then manufacturing is simpler, but threshold voltage variations increase
Solution Approach 1:
The patent introduces an oxidation suppressing layer with spatially varying properties to control the local thickness of the horizontal gate insulating layer. The oxidation suppressing layer is configured differently in the first region (under first functional circuits) compared to the second region (under second functional circuits), enabling precise local control of gate insulating layer thickness to achieve uniformity across different regions while managing the associated structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables increased integration density and efficient data storage by maintaining a uniform thickness of the horizontal gate insulating layer across the cell array and connection regions, reducing variations in threshold voltage and enhancing memory device performance.
Implementation Method 1
A doped oxidation suppressing material may be included in the substrate and may extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively
Implementation Method 2
A three-dimensional semiconductor memory device can include an oxidation suppressing layer in a substrate and a plurality of stacks on the oxidation suppressing layer
Data Source
AI summary
A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit device, where the first functional circuits has a substantially constant top surface level across the first region and having a second region reserved for second functional circuits of the vertically integrated circuit device and spaced apart from the first region. The second functional circuits can have a varied top surface level across the second region. A doped oxidation suppressing material can be included in the substrate and can extend from the first region to the second region at an interface of the substrate with the first functional circuits and the second functional circuits, respectively.