Oxide Semiconductor Array Substrate Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The existing array substrates for LCDs and OLEDs face issues with parasitic capacitance and the complexity of mask processes due to the need for multiple mask steps, which increases production time, cost, and error rates, particularly when using oxide semiconductor layers that require etch stoppers for protection during etching.
Innovation Solution
A method is introduced to reduce parasitic capacitance and the number of mask processes by forming a conductive connection pattern between the oxide semiconductor layer and the source and drain electrodes, allowing them to be spaced apart from the gate electrode, and using an etch stopper to prevent damage to the oxide semiconductor layer, while also simplifying the fabrication process through a reduced number of mask steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple mask processes are used to form etch stoppers and connection patterns, then the oxide semiconductor layer is protected from damage, but the production time and manufacturing complexity increase
Solution Approach 1:
The patent combines the formation of the etch stopper layer and connection patterns into a single mask process. The etch stopper layer is formed first to protect the oxide semiconductor layer, then connection patterns are formed in the same masking step, eliminating the need for separate mask processes and reducing manufacturing complexity while maintaining protection of the oxide semiconductor layer
Solution Approach 2:
The etch stopper layer is formed in advance before the connection patterns, ensuring that the oxide semiconductor layer is protected from etching damage during the formation of connection patterns. This preliminary protective action allows subsequent processing to proceed without risking damage to the sensitive oxide semiconductor layer
2Area of stationary object
If electrodes are positioned close to the gate electrode, then device area is reduced, but parasitic capacitance increases
Solution Approach 1:
The etch stopper layer serves as an intermediary between the connection patterns and the oxide semiconductor layer, allowing the connection patterns to be positioned closer to the gate electrode without directly contacting the sensitive oxide semiconductor layer. This intermediary structure enables reduced device area while maintaining low parasitic capacitance by preventing direct overlap between conductive elements
Data Source
Figure 1~2
Figure 3
Figure 4A
AI summary
An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes.