3D Oxide-Bonded Semiconductor Structure for Dense Vertical Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in constructing high-density connections between layers of 3D stacked semiconductor chips due to misalignment issues and the degradation of wiring layers when forming transistor layers at high temperatures, leading to limited connectivity and performance degradation.
Innovation Solution
The implementation of a semiconductor device with a first silicon layer, isolation layer, and metal layers, where the isolation layer includes an oxide-to-oxide bond surface, and the use of optical annealing to repair defects and activate dopants without damaging underlying metal interconnects, allowing for the construction of high-aspect ratio vias and monocrystalline silicon layers for improved connectivity and heat management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistor layers are constructed at high temperatures (>700°C) to improve transistor performance and density, then transistor functionality is improved, but underlying wiring layers are damaged
Solution Approach 1:
The patent divides the semiconductor structure into separate crystalline layers that can be independently processed. Each layer can be fabricated at its optimal temperature range without affecting other layers, resolving the conflict between high-temperature transistor processing and low-temperature wiring integrity
Solution Approach 2:
The patent introduces intermediate bonding layers and isolation structures between the transistor layers and wiring layers. These intermediary elements protect the sensitive wiring from thermal damage during high-temperature transistor processing while maintaining electrical connectivity
2Speed
If 3D stacking is implemented to reduce wire lengths and improve connectivity, then wiring delay is reduced, but misalignment issues and manufacturing complexity increase
Solution Approach 1:
The patent transitions from 2D planar integration to 3D stacked architecture, organizing transistor layers and wiring layers in vertical dimensions. This enables shorter interconnect paths and improved connectivity while the independent layer processing approach manages the increased manufacturing complexity
Solution Approach 2:
The patent performs preliminary processing of each crystalline layer independently before stacking, including dopant activation and defect repair. This preliminary action ensures each layer is optimized before assembly, reducing alignment issues and simplifying the overall manufacturing process
3Quantity of substance
If oxide-to-oxide bonding is used to bond silicon layers to achieve high-density connections, then connectivity density is improved, but bonding precision and misalignment sensitivity increase
Solution Approach 1:
The oxide-to-oxide bonding interface exhibits self-aligning properties where the bonding process itself facilitates precise alignment. The chemical reactivity and surface properties of the oxide layers enable automatic positioning and high-precision bonding without requiring external alignment mechanisms
Solution Approach 2:
The patent modifies the physical and chemical parameters of the oxide bonding surfaces, including surface preparation methods and bonding temperature control. These parameter changes optimize the bonding process to achieve high connection density while maintaining manufacturing precision and reducing misalignment sensitivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the construction of high-density connections and maintains the reliability of underlying wiring layers, enhancing the performance and density of 3D stacked semiconductor chips while overcoming temperature-related misalignment issues.
Implementation Method 1
the isolation layer includes an oxide to oxide bond surface
Implementation Method 2
the use of optical annealing to repair defects and activate dopants without damaging underlying metal interconnects
Data Source
AI summary
A semiconductor device, the device including: a first silicon layer including first single crystal silicon; an isolation layer disposed over the first silicon layer; a first metal layer disposed over the isolation layer; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the isolation layer includes an oxide to oxide bond surface, where the plurality of transistors include a second single crystal silicon region; and a third metal layer disposed over the first level, where a typical first thickness of the third metal layer is at least 50% greater than a typical second thickness of the second metal layer.