3D Semiconductor Device with Oxide Bonds and Single Crystal Transistors
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Solution Overview
Problem
Current 3D stacked semiconductor chip technologies face challenges in achieving high-density connections between layers due to misalignment issues and the need for high-temperature processing, which damages lower wiring layers and limits connectivity.
Innovation Solution
The development of methods for constructing 3D memory devices with single crystal transistors and oxide-to-oxide bonding, allowing for high-density connectivity and alignment with less than 40 nm error, using techniques such as ion-cut layer transfer and replacement gate processing to maintain transistor performance across layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature processing (>700°C) is used to construct transistor layers, then transistor performance is improved, but lower wiring layers are damaged
Solution Approach 1:
The patent divides the 3D stacked structure into separate processing stages: bottom wiring layers are constructed first at low temperatures, then isolated with protective layers, and top transistor layers are constructed separately at high temperatures before bonding. This segmentation allows each layer to be processed at optimal temperatures without damaging other layers.
Solution Approach 2:
The bottom wiring layers and isolation layers are constructed in advance before the top transistor layers are formed. This preliminary action ensures that temperature-sensitive lower layers are already in place and protected before high-temperature processing occurs on the upper layers.
2Device complexity
If wafer bonding is used to connect stacked layers, then 3D integration is achieved, but misalignment errors limit connectivity density
Solution Approach 1:
The patent incorporates alignment margin features and tolerance-compensating structures in the design phase to cushion against misalignment errors. Landing pads and contact regions are designed with sufficient margin to accommodate expected alignment variations, ensuring reliable connectivity despite bonding inaccuracies.
3Quantity of substance
If contact size is reduced to increase connectivity density, then connection density improves, but alignment tolerance decreases
Solution Approach 1:
The patent optimizes contact and landing pad dimensions to achieve optimal connectivity density while maintaining adequate alignment tolerance. By carefully selecting and adjusting geometric parameters such as contact diameter, landing pad area, and spacing, the design achieves high connection density without sacrificing robustness to alignment errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the construction of 3D semiconductor devices with high-density connections and improved transistor performance, overcoming the limitations of existing technologies by maintaining transistor integrity and connectivity across layers.
Implementation Method 1
the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds
Data Source
AI summary
A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal channel, where at least one of the plurality of transistors includes a second single crystal channel, where the second single crystal channel is disposed above the first single crystal channel, where at least one of the plurality of transistors includes a third single crystal channel, where the third single crystal channel is disposed above the second single crystal channel, where at least one of the plurality of transistors includes a fourth single crystal channel, and where the fourth single crystal channel is disposed above the third single crystal channel; and at least one region of oxide to oxide bonds.