Oxide Transistor Substrate Buffer Layout for Hydrogen Mobility Control
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Solution Overview
Problem
Current transistors in display devices face limitations in charge mobility and manufacturing complexity, with amorphous silicon offering low performance and polycrystalline silicon being costly and complicated, while oxide semiconductors are affected by hydrogen from adjacent layers.
Innovation Solution
A transistor substrate with distinct buffer layers of silicon nitride and silicon oxide under different transistors, allowing for increased charge mobility in one transistor while minimizing hydrogen impact on another, optimizing channel region lengths for improved performance and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide semiconductor layers are used to increase charge mobility, then charge mobility is improved, but hydrogen from adjacent insulating layers degrades performance
Solution Approach 1:
The substrate is divided into first and second regions with different buffer layer configurations. The first region contains both first buffer layer (silicon nitride) and second buffer layer (silicon oxide), while the second region contains only the second buffer layer. This segmentation allows different transistors to have different hydrogen environments, enabling high charge mobility where needed while avoiding hydrogen contamination in other areas.
Solution Approach 2:
Different buffer layer structures are applied to different regions: the first region has a dual-buffer structure (silicon nitride + silicon oxide) to provide high charge mobility, while the second region has only the silicon oxide buffer layer to avoid hydrogen contamination. This local quality approach optimizes each region for its specific function.
2Reliability
If polycrystalline silicon is used to achieve high charge mobility, then charge mobility is improved, but manufacturing cost increases and process complexity increases
Solution Approach 1:
The patent changes the material parameters of the buffer layers (using silicon nitride and silicon oxide with specific properties) to achieve high charge mobility in oxide semiconductor transistors without requiring the silicon crystallization step needed for polycrystalline silicon. This parameter change maintains high performance while simplifying the manufacturing process.
3Manufacturing precision
If more transistors are placed in pixel portions to increase resolution, then resolution is improved, but the area required for driving portions increases
Solution Approach 1:
The first buffer layer is selectively formed only in the first region (driving portion) while the second buffer layer covers both first and second regions. This allows the driving portion transistors to have enhanced charge mobility properties without requiring additional area, enabling more transistors to be packed into the pixel portions for higher resolution.
Solution Approach 2:
The substrate is segmented into first and second regions with different buffer layer configurations, allowing independent optimization of driving portion and pixel portion characteristics. This segmentation enables compact driving portions that can support higher resolution displays.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances charge mobility in some transistors, reduces the area required for driving portions, and increases the number of transistors in pixel portions, resulting in a display device with higher resolution and reduced manufacturing complexity.
Implementation Method 1
charge mobility of the first oxide semiconductor layer may increase due to hydrogen supplied from the first buffer layer
Implementation Method 2
The buffer layer may prevent impurities such as oxygen and moisture from permeating through the substrate
Data Source
AI summary
A transistor substrate may include a substrate including a first region and a second region, a first buffer layer disposed in the first region on the substrate and including silicon nitride, a second buffer layer disposed in the first region and the second region on the first buffer layer and including silicon oxide, a first transistor disposed in the first region on the second buffer layer and including a first oxide semiconductor layer and a first gate electrode overlapping the first oxide semiconductor layer, and a second transistor disposed in the second region on the second buffer layer and including a second oxide semiconductor layer and a second gate electrode overlapping the second oxide semiconductor layer.