Oxide Capping for 2D Transistor Channels Against Oxidation
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Solution Overview
Problem
The deployment of 2D materials in transistor structures is hindered by their sensitivity to fabrication processes, leading to oxidation and degradation of material properties, which affects the quality and performance of transistor devices.
Innovation Solution
A capping layer, composed of materials like HfOx, SiOx, ZrOx, YxOz, AlxOz, TaxOz, NbO, NbOx, or TiOx, is applied directly on the 2D channel material to protect it during subsequent processing steps such as lithography and etch, with optional carbon doping for enhanced protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 2D materials are used in transistor structures to achieve advanced scaling, then device performance and miniaturization are improved, but the materials become sensitive to fabrication processes leading to oxidation and degradation
Solution Approach 1:
A capping layer is introduced as an intermediary protective barrier between the 2D channel material and the fabrication environment. This capping layer prevents direct exposure of the sensitive 2D material to oxidizing conditions during lithography and etch processes, thereby maintaining material integrity while enabling advanced device scaling
Solution Approach 2:
The capping layer is applied in advance before subsequent fabrication steps that could cause oxidation. By pre-protecting the 2D material surface with the capping layer, the material is shielded from harmful environmental exposure during critical processing steps such as lithography and etch
2Object-affected harmful factors
If a capping layer is applied to protect 2D channel material, then oxidation and surface damage are prevented, but device structure complexity increases
Solution Approach 1:
The capping layer is implemented as a thin film structure that provides effective protection against oxidation and surface damage. This thin film approach maintains the compactness of the transistor structure while delivering the necessary protective function, thereby limiting the increase in overall device complexity
Data Source
AI summary
Devices, transistor structures, systems, and techniques are described herein related to field effect transistors having one or more metal chalcogenide nanoribbons coupled to a source and a drain. Channel regions of the metal chalcogenide nanoribbons are coupled to a gate structure between the source and the drain. The metal chalcogenide nanoribbons are capped with a layer including an oxide of a metal or metalloid element, optionally doped with or including carbon.


