Oxide Semiconductor Channel Thickness Control During Electrode Etching
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Solution Overview
Problem
Semiconductor devices using oxide semiconductors for channels face challenges in achieving stable electrical characteristics due to variations in channel thickness, which affect mobility and yield, especially when forming source and drain electrodes.
Innovation Solution
A semiconductor device with a polycrystalline oxide semiconductor layer having a thickness difference of 5 nm or less between regions overlapping source/drain electrodes and those in contact with the interlayer insulating layer, utilizing a metal oxide layer as a mask for etching and annealing to enhance etching resistance and control channel thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an oxide semiconductor layer is used for the channel, then field-effect mobility is improved (20 cm2/Vs or more), but variations in channel thickness occur, deteriorating electrical characteristic stability
Solution Approach 1:
The patent applies local quality by forming a metal oxide layer selectively in regions overlapping source/drain electrodes while maintaining a different structure in the channel region. This creates spatially varying properties: the metal oxide layer provides etching resistance where needed, while the oxide semiconductor layer maintains uniform thickness in the channel region for stable electrical characteristics.
Solution Approach 2:
The metal oxide layer is formed beforehand as a protective mask before etching the source/drain electrodes. This preliminary action prevents excessive etching of the oxide semiconductor layer in critical regions, ensuring uniform channel thickness is maintained throughout the manufacturing process.
2Speed
If the oxide semiconductor layer thickness is reduced to improve device performance, then mobility increases, but etching resistance deteriorates, making manufacturing difficult
Solution Approach 1:
The metal oxide layer serves as an intermediary protective layer between the etching process and the thin oxide semiconductor channel layer. It absorbs the etching impact, allowing the channel layer to maintain its thin profile for high mobility while still providing sufficient etching resistance during manufacturing.
Solution Approach 2:
The structure combines metal oxide and oxide semiconductor materials with complementary properties. The metal oxide provides high etching resistance, while the oxide semiconductor provides high mobility, creating a composite structure that achieves both manufacturing ease and device performance.
3Ease of manufacture
If source and drain electrodes are formed by conventional etching, then electrode formation is achieved, but the oxide semiconductor layer is excessively etched, causing thickness variations
Solution Approach 1:
The metal oxide layer is formed beforehand as a cushioning protective layer in regions where etching will occur. This layer absorbs the excessive etching that would otherwise damage the oxide semiconductor channel, preserving channel thickness uniformity while still allowing electrode formation to proceed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves stable electrical characteristics with field-effect mobility of 20 cm2/Vs or more, improving yield and reducing variations in channel thickness, thereby enhancing the reliability and performance of the semiconductor device.
Implementation Method 1
utilizing a metal oxide layer as a mask for etching and annealing to enhance etching resistance
Implementation Method 2
utilizing a metal oxide layer as a mask for etching and annealing
Data Source
AI summary
A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, a metal oxide layer over the gate insulating layer, an oxide semiconductor layer having a polycrystalline structure over the metal oxide layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer, the interlayer insulating layer covering the source electrode and the drain electrode, wherein the oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer, and a difference between a thickness of the first region and a thickness of the second region is 5 nm or less.