Oxide Semiconductor Channel Gradient for 3D Ferroelectric Memory
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in achieving high carrier mobility and reducing manufacturing defects, particularly in the context of three-dimensional memory arrays.
Innovation Solution
The implementation of a three-dimensional memory array with vertically stacked memory cells, each comprising a thin film transistor (TFT) with a ferroelectric gate dielectric layer and an oxide semiconductor channel region. The oxide semiconductor channel region is designed with at least three different regions of varying indium concentrations, optimizing carrier mobility and reducing process damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniform indium concentration is used in the oxide semiconductor channel region, then the manufacturing process is simple, but carrier mobility is limited and manufacturing defects increase
Solution Approach 1:
The oxide semiconductor channel region is divided into multiple regions with different indium concentrations: a first region with higher indium concentration to enhance carrier mobility, a second region with lower indium concentration to reduce defects, and a third intermediate region to minimize electron scattering. This local differentiation of material properties resolves the contradiction between achieving high carrier mobility and maintaining manufacturing simplicity.
Solution Approach 2:
The indium concentration parameter is varied spatially within the oxide semiconductor channel region. By changing the indium concentration from the first region (higher) through the third region (intermediate) to the second region (lower), the patent optimizes both carrier mobility and defect reduction, transforming a single-parameter uniform structure into a multi-parameter gradient structure.
2Reliability
If high indium concentration is used throughout the channel region, then carrier mobility increases, but manufacturing defects and electron scattering increase
Solution Approach 1:
The patent applies local quality by concentrating higher indium concentration in the first region where it is most needed for carrier mobility, while using lower indium concentration in the second region to minimize manufacturing defects. The third region serves as a transition zone, creating a spatially differentiated structure that locally optimizes for different requirements.
Solution Approach 2:
The patent converts the potentially harmful effect of high indium concentration (which causes defects and electron scattering) into a beneficial localized feature. By confining high indium concentration to specific regions and using gradient transitions, the harmful effects are minimized while retaining the mobility benefits where needed.
3Quantity of substance
If vertically stacked memory cells are implemented, then memory density increases, but manufacturing precision requirements increase
Solution Approach 1:
The oxide semiconductor layer is segmented into multiple regions with different indium concentrations through sequential deposition processes. This segmentation allows for precise control of material properties in different zones, enabling the fabrication of complex vertically stacked memory cells with controlled carrier mobility and defect distribution.
Solution Approach 2:
The patent performs preliminary actions by depositing oxide semiconductor layers with different indium concentrations in a predetermined sequence before final device assembly. This preliminary differentiation of material properties simplifies subsequent manufacturing steps and ensures precise control over the final device characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances carrier mobility, reduces electron scattering, and minimizes manufacturing defects, thereby improving the overall performance and density of the memory array.
Implementation Method 1
each comprising a thin film transistor (TFT) with a ferroelectric gate dielectric layer
Implementation Method 2
The oxide semiconductor channel region is designed with at least three different regions of varying indium concentrations, optimizing carrier mobility
Implementation Method 3
reduces electron scattering, and minimizes manufacturing defects
Data Source
AI summary
A memory cell includes a ferroelectric (FE) material contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the FE material is disposed between the OS layer and the word line. The OS layer comprises: a first region adjacent the FE material, the first region having a first concentration of a semiconductor element; a second region adjacent the source line, the second region having a second concentration of the semiconductor element; and a third region between the first region and the second region, the third region having a third concentration of the semiconductor element, the third concentration is greater than the second concentration and less than the first concentration.