Oxide Semiconductor Channel Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices are miniaturized, leakage current through the channel region in DRAM devices with a 1T-1C structure increases, necessitating a reduction in leakage current while maintaining excellent electrical characteristics.
Innovation Solution
A semiconductor device design incorporating a mold insulating layer with openings, channel layers with vertical and horizontal extension portions, passivation layers, and a gate insulating layer, utilizing oxide semiconductor materials to reduce leakage current and enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If device size is reduced through miniaturization, then device density and integration are improved, but leakage current through the channel region increases
Solution Approach 1:
The patent changes the material parameter of the channel layer from conventional semiconductor materials to oxide semiconductor materials. This material parameter change fundamentally alters the electrical characteristics, enabling low leakage current even in miniaturized devices. The oxide semiconductor channel layer maintains excellent electrical characteristics at reduced device sizes where conventional materials would exhibit excessive leakage.
2Object-generated harmful factors
If oxide semiconductor material is used in the channel layer, then leakage current is reduced, but manufacturing complexity increases due to additional layers and processes
Solution Approach 1:
The patent segments the device structure into distinct functional layers: oxide semiconductor channel layer, passivation layer, gate insulating layer, and mold insulating layer with openings. Each layer serves a specific purpose and can be manufactured using standardized semiconductor processing techniques. This segmentation allows the complex oxide semiconductor device to be built through modular, sequential fabrication steps.
Solution Approach 2:
The passivation layer acts as an intermediary between the oxide semiconductor channel layer and the gate insulating layer. This intermediate layer facilitates the integration of oxide semiconductor material into conventional semiconductor manufacturing processes, enabling the channel layer to be formed and protected before subsequent gating and insulating steps are applied.
3Reliability
If channel layer includes vertical and horizontal extension portions, then electrical characteristics are improved, but manufacturing precision requirements increase
Solution Approach 1:
The mold insulating layer with openings is formed beforehand to define and guide the formation of the channel layer's vertical and horizontal extension portions. This preliminary structuring establishes precise geometric constraints that direct subsequent material deposition and patterning steps, ensuring accurate formation of the extended channel regions without requiring ultra-precise direct patterning.
Data Source
AI summary
A semiconductor device includes a plurality of bit lines arranged on a substrate and extending in a first horizontal direction, a mold insulating layer arranged on the bit lines and including a plurality of openings extending in a second horizontal direction, respectively, a plurality of channel layers respectively arranged on the bit lines and including a first vertical extension portion, in each opening of the mold insulating layer, a plurality of passivation layers respectively arranged on each vertical extension portion, a gate insulating layer arranged to face each vertical extension portion with each passivation layer therebetween, and a plurality of word lines extending in the second horizontal direction on the gate insulating layer and including first word lines respectively arranged on a first sidewall of each opening of the mold insulating layer and second word lines respectively arranged on a second sidewall of each opening of the mold insulating layer.