Oxide Semiconductor Vertical Channel Layout for Low Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving small parasitic capacitance, favorable electrical characteristics, high on-state current, miniaturization, high integration, high resolution, high aperture ratio, reliability, low power consumption, and high-speed operation, particularly in transistors with oxide semiconductor layers.
Innovation Solution
The semiconductor device incorporates an oxide semiconductor layer, conductive layers, and insulating layers with specific structural features such as depressed portions and opening portions to reduce parasitic capacitance, enhance electrical characteristics, and increase on-state current, while allowing for miniaturization and high integration, including a halogen element in the insulating layers and a metal oxide channel formation region to improve reliability and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional transistor structure is used, then the device can be manufactured with standard processes, but the parasitic capacitance is large which limits high-speed operation
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical structure where the channel extends in the depth direction rather than only in the plane. This dimensional change allows the channel length to be effectively increased while maintaining a compact footprint, thereby reducing parasitic capacitance between source and drain regions while enabling higher operation speeds
Solution Approach 2:
The transistor channel is divided into multiple segments along the depth direction, with each segment forming a portion of the vertical channel. This segmentation allows for optimized electrical characteristics at each level while collectively achieving reduced parasitic capacitance and improved high-speed performance
2Productivity
If the transistor size is reduced for miniaturization, then the integration density increases, but the on-state current decreases
Solution Approach 1:
By extending the channel in the vertical depth direction rather than reducing it in the plane, the patent achieves miniaturization in the lateral dimensions (increasing integration density) while maintaining or enhancing the effective channel length through vertical extension, thereby preserving on-state current despite reduced device footprint
Solution Approach 2:
The vertical channel structure nests multiple functional regions within the depth of the device, allowing the channel to fold back on itself or extend through multiple layers. This nested arrangement increases the effective channel length and current-carrying capacity within a minimized lateral footprint, achieving both miniaturization and maintained on-state current
3Speed
If the channel length is increased to reduce parasitic capacitance, then the high-speed operation improves, but the device area increases
Solution Approach 1:
The patent resolves this contradiction by routing the channel in the vertical depth dimension rather than extending it laterally. This allows the effective channel length to be increased for reduced parasitic capacitance and improved high-speed operation, while the lateral device area remains compact due to the vertical orientation of the channel structure
Data Source
AI summary
A semiconductor device includes an oxide semiconductor layer, first to third conductive layers, and first to third insulating layers. The first conductive layer includes a first depressed portion. The first insulating layer over the first conductive layer and the second conductive layer over the first insulating layer include a first opening portion overlapping with the first depressed portion. The oxide semiconductor layer is in contact with a top surface of the second conductive layer, bottom and side surfaces of the first depressed portion, a side surface of the second conductive layer, and a side surface of the first insulating layer. The second insulating layer is positioned inside the oxide semiconductor layer in the first opening portion. The third insulating layer covers top and side surfaces of the oxide semiconductor layer over the first insulating layer, and includes a second opening portion overlapping with the first opening portion.