Oxide Semiconductor Channel Stack for Low-Leakage Memory Cells
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Solution Overview
Problem
Current semiconductor memory devices face limitations in integration density and performance due to high equipment costs and poor interface characteristics between oxide semiconductor channel layers and conductive lines, leading to increased leakage currents.
Innovation Solution
A semiconductor memory device is designed with a channel layer comprising sequentially stacked oxide semiconductor layers, where the first layer has higher crystallinity for improved carrier mobility and interface characteristics, and dielectric layers with varying dielectric constants to reduce leakage current and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If oxide semiconductor channel layers are used, then integration density is improved, but interface characteristics deteriorate leading to increased leakage current
Solution Approach 1:
The channel layer is segmented into multiple oxide semiconductor layers with different crystallinities. The first oxide semiconductor layer has higher crystallinity for low leakage current, while the second oxide semiconductor layer has lower crystallinity for good interface characteristics with the conductive line. This segmentation allows each layer to optimize for its specific function, resolving the contradiction between integration density and interface characteristics.
Solution Approach 2:
Different regions of the channel layer are assigned different local qualities in terms of crystallinity. The first oxide semiconductor layer positioned adjacent to the conductive line has high crystallinity to minimize leakage, while the second oxide semiconductor layer has lower crystallinity to ensure good interface characteristics. This local quality differentiation resolves the contradiction by optimizing each region for its specific requirement.
2Object-generated harmful factors
If high crystallinity oxide semiconductor layer is used, then leakage current is reduced, but interface characteristics with conductive line deteriorate
Solution Approach 1:
The channel layer is divided into two oxide semiconductor layers with different crystallinities. The first layer has high crystallinity to reduce leakage current, while the second layer has lower crystallinity to provide good interface characteristics with the conductive line. This segmentation allows simultaneous optimization for both low leakage and good interface characteristics.
Solution Approach 2:
The channel layer is constructed as a composite of two oxide semiconductor layers with different crystalline properties. The first oxide semiconductor layer provides low leakage current through high crystallinity, while the second oxide semiconductor layer ensures good interface characteristics through lower crystallinity. This composite structure resolves the contradiction by combining materials with complementary properties.
Data Source
AI summary
A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.