Semiconductor devices
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Solution Overview
Problem
Existing memory devices with vertical channel transistors face challenges in enhancing the reliability and electrical characteristics of oxide semiconductor channels.
Innovation Solution
The semiconductor device incorporates a channel structure comprising both amorphous and crystalline oxide semiconductors, with the crystalline channel partially overlapping the gate electrode, and includes an etch stop pattern containing hydrogen to facilitate crystallization, thereby increasing carrier concentration and on-current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an amorphous oxide semiconductor channel is used, then the manufacturing process is simpler, but the carrier concentration and on-current are lower
Solution Approach 1:
The channel is divided into two distinct regions: an amorphous oxide semiconductor region and a crystalline oxide semiconductor region. This segmentation allows each region to contribute its unique properties - the amorphous region provides ease of manufacture while the crystalline region provides high carrier concentration and reliability, thus resolving the contradiction between manufacturing simplicity and electrical characteristics reliability.
Solution Approach 2:
The channel structure combines amorphous oxide semiconductor and crystalline oxide semiconductor materials to form a composite channel. This composite structure integrates the advantages of both material phases - the manufacturing benefits of amorphous materials with the superior electrical properties of crystalline materials, thereby achieving both ease of manufacture and high reliability.
2Reliability
If a crystalline oxide semiconductor channel is used, then the carrier concentration and on-current are higher, but the manufacturing process becomes more complex
Solution Approach 1:
The crystalline oxide semiconductor is localized to specific regions within the channel rather than requiring the entire channel to be crystalline. This local quality approach allows the high-performance crystalline material to be applied only where needed (in contact with the amorphous channel) to enhance carrier concentration, while the rest of the channel maintains the manufacturing simplicity of amorphous materials.
3Productivity
If the channel structure is optimized for higher on-current, then the device performance improves, but the device complexity increases
Solution Approach 1:
The amorphous oxide semiconductor channel is formed first as a base layer, and then the crystalline oxide semiconductor is subsequently introduced in contact with it. This preliminary action sequence simplifies the overall process by establishing the easy-to-manufacture amorphous channel first, then adding the performance-enhancing crystalline component, rather than requiring complex simultaneous formation of both structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the on-current of the vertical channel transistor by leveraging the higher carrier concentration of crystalline oxide semiconductors and improves the reliability of the electrical characteristics.
Implementation Method 1
includes an etch stop pattern containing hydrogen to facilitate crystallization, thereby increasing carrier concentration and on-current
Data Source
AI summary
A semiconductor device includes bit lines, gate electrodes, a gate insulation pattern and a channel structure on a substrate. Each of the bit lines extends in a first direction, and the bit lines may be spaced apart from each other in a second direction. The gate electrodes are spaced apart from each other in the first direction, and each of the gate electrodes extends in the second direction. For each of the gate electrodes, a gate insulation pattern is formed on a sidewall in the first direction of the gate electrode, and a channel structure is formed on a sidewall in the first direction of the gate insulation pattern. The channel structure includes a first amorphous channel including an amorphous oxide semiconductor and a first crystalline channel including a crystalline oxide semiconductor and contacting an upper surface of the first amorphous channel.