Polycrystalline Oxide Semiconductor Channel for Photodegradation Stability
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Solution Overview
Problem
Semiconductor devices using oxide semiconductor films face issues with photodegradation, and there is a need for further suppression of this degradation.
Innovation Solution
A semiconductor device is designed with a polycrystalline oxide semiconductor layer having a specific S value range (1.5 V/dec to 2.5 V/dec) and manufacturing process that includes forming a gate electrode, gate insulating layers, patterning a conductive film to create source and drain electrodes, and performing annealing treatments to enhance the oxide semiconductor layer, ensuring stable electrical characteristics and reduced photodegradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an oxide semiconductor film is used for the channel, then field effect mobility is improved compared to amorphous silicon, but photodegradation occurs and electrical characteristics become unstable
Solution Approach 1:
The patent applies parameter changes by controlling the S value (subthreshold swing) within a specific range of 1.5 to 2.5 V/dec and adjusting the channel region thickness to 5 nm or more. These parameter optimizations resolve the contradiction by achieving both high field effect mobility and stable electrical characteristics, eliminating photodegradation issues while maintaining the advantages of oxide semiconductor materials.
2Speed
If the oxide semiconductor layer is made thinner to reduce capacitance, then switching speed is improved, but electrical characteristic stability deteriorates due to increased photodegradation
Solution Approach 1:
The patent resolves this contradiction by optimizing the channel region thickness to 5 nm or more and controlling the S value within 1.5 to 2.5 V/dec. This parameter optimization allows the device to achieve fast switching speed while maintaining electrical characteristic stability and suppressing photodegradation, rather than simply making the layer thinner.
3Speed
If annealing treatment is performed to improve crystallinity, then field effect mobility is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies parameter changes by controlling the S value within 1.5 to 2.5 V/dec and the channel thickness at 5 nm or more, which allows achieving high field effect mobility through optimized material properties and structure rather than complex multi-step annealing processes. The manufacturing method integrates necessary heat treatments into the existing process flow without adding significant complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves improved field-effect mobility and suppressed photodegradation, maintaining stable electrical characteristics and high voltage resistance by controlling the S value and channel region thickness.
Implementation Method 1
performing an annealing treatment on the oxide semiconductor layer whose surface is exposed from the source electrode and the drain electrode after forming the source electrode and the drain electrode
Data Source
AI summary
A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer having a polycrystalline structure over the gate insulating layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer covering the source electrode and the drain electrode and in contact with the oxide semiconductor layer. An S value is greater than or equal to 1.5 V/dec and less than or equal to 2.5 V/dec.