Semiconductor device and method of manufacturing the same
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Solution Overview
Problem
The short-channel effect in semiconductor devices leads to issues such as threshold voltage variation, carrier velocity saturation, and deterioration of subthreshold characteristics due to the reduction in size, making it difficult to control the threshold voltage and increase the contact area between the channel and electrode, which affects the performance and integration of integrated circuit devices.
Innovation Solution
A semiconductor device is designed with a buffer layer, including silicide materials like WSix, RuSix, and TiSix, between the metal oxide and oxide channel, and optionally between the upper and oxide channel, to reduce side reactions and interface resistance, thereby improving contact characteristics and suppressing the short-channel effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the transistor size is reduced to increase integration density, then the degree of integration is improved, but the short-channel effect worsens causing threshold voltage variation and carrier velocity saturation
Solution Approach 1:
The patent transitions from a planar transistor structure to a vertical channel structure, changing the dimensional orientation of the current flow. This vertical configuration allows the channel to extend perpendicular to the substrate, enabling better electrostatic control of the channel by the gate while maintaining small footprint area, thus improving integration density without suffering from short-channel effects
Solution Approach 2:
The gate electrode completely surrounds the oxide channel in a wrap-around configuration, with the gate insulating layer positioned between the gate electrode and the channel. This nested structure provides enhanced electrostatic control over the channel, effectively suppressing short-channel effects and improving threshold voltage control while maintaining compact device dimensions
2Volume of moving object
If the contact area between gate electrode and channel is reduced due to smaller transistor size, then the transistor size is improved, but the power efficiency deteriorates
Solution Approach 1:
The vertical channel structure extends the channel length in the vertical dimension rather than reducing horizontal dimensions. This allows the transistor to maintain a small planar footprint for high integration while providing sufficient channel length for effective gate control and acceptable power efficiency through the vertical extension of the channel region
3Productivity
If the channel length is reduced to improve integration, then the integration density is improved, but the subthreshold characteristics deteriorate
Solution Approach 1:
The gate electrode completely surrounds the oxide channel with the gate insulating layer positioned between them, creating a wrap-around structure. This nested configuration provides superior electrostatic control over the channel, effectively suppressing short-channel effects and maintaining good subthreshold characteristics even when the channel length is reduced for higher integration density
Solution Approach 2:
The vertical channel structure allows the channel to extend in the vertical dimension perpendicular to the substrate, enabling sufficient effective channel length for good subthreshold characteristics while maintaining a small planar footprint for high integration density
Data Source
AI summary
Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a lower electrode on a substrate, a metal oxide on the lower electrode, a buffer on the metal oxide, an oxide channel in the buffer, a gate insulating layer in the oxide channel, a gate electrode in the gate insulating layer, and an upper electrode on the gate electrode, and the buffer may include a silicide material.