Polycrystalline Oxide Semiconductor Channel Thickness Control
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Solution Overview
Problem
Conventional semiconductor devices with oxide semiconductor films face challenges in controlling the shape of the oxide semiconductor film due to low etching resistance, leading to variations in electrical characteristics and reduced yield, especially in large-area substrates.
Innovation Solution
A semiconductor device with a polycrystalline oxide semiconductor layer having a thickness difference of less than or equal to 5 nm between overlapping and non-overlapping regions, achieved through a manufacturing process involving gate electrode formation, gate insulating layer deposition, oxide semiconductor layer patterning, and interlayer insulating layer coverage, which enhances etching resistance and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an oxide semiconductor film is used for the channel, then higher mobility and simpler fabrication are achieved, but etching resistance is low leading to shape control difficulties
Solution Approach 1:
The invention changes the structural parameter of the oxide semiconductor layer by forming a thickness difference between the channel region and source/drain regions. This parameter change enables better shape control during etching while maintaining the high mobility benefits of oxide semiconductors, resolving the contradiction between reliability and manufacturing precision.
Solution Approach 2:
The invention applies local quality by creating different thicknesses of the oxide semiconductor layer in different regions: a thinner thickness in the channel region for high mobility and a thicker thickness in the source/drain regions for improved etching resistance and shape control. This local differentiation resolves the contradiction between electrical characteristics stability and shape control.
2Speed
If the oxide semiconductor film thickness is reduced to improve mobility, then field-effect mobility increases, but etching resistance decreases further
Solution Approach 1:
The invention implements local quality by varying the oxide semiconductor layer thickness across different functional regions. The channel region has a first thickness optimized for high field-effect mobility, while the source/drain regions have a second thickness (greater than the first) that provides sufficient etching resistance. This spatial differentiation resolves the contradiction between speed and reliability.
Solution Approach 2:
The invention adds a dimensional aspect to the oxide semiconductor layer structure by creating a thickness gradient. This dimensional change allows the layer to simultaneously achieve thinness for high mobility in the channel and sufficient thickness for etching resistance in the source/drain regions, resolving the contradiction between field-effect mobility and etching resistance.
3Ease of manufacture
If conventional oxide semiconductor fabrication is used, then manufacturing simplicity is maintained, but yield decreases due to shape variations in large-area substrates
Solution Approach 1:
The invention introduces a thickness parameter variation in the oxide semiconductor layer that can be achieved through existing low-temperature polysilicon fabrication techniques. This parameter change improves yield by ensuring consistent shape control across large-area substrates while maintaining the ease of manufacture associated with simple fabrication processes.
Solution Approach 2:
The invention performs preliminary action by forming the thickness-differentiated oxide semiconductor layer structure before subsequent processing steps. This preliminary structuring ensures that the oxide semiconductor maintains its shape integrity during etching and subsequent manufacturing steps, preventing yield loss in large-area substrates while keeping the overall fabrication process simple.
Data Source
AI summary
A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer having a polycrystalline structure over the gate insulating layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer. The interlayer insulating layer covers the source electrode and the drain electrode. The oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer. A difference between a film thickness of the first region and a film thickness of the second region is less than or equal to 5 nm.