Oxide Semiconductor CMOS TFT Structure With Shared Gate Insulator
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Solution Overview
Problem
A suitable configuration for a CMOS structure that includes both n-type and p-type oxide semiconductor TFTs has not been established, which is necessary for achieving lower voltages and reduced power consumption in semiconductor devices.
Innovation Solution
A semiconductor device comprising a substrate with a first n-type oxide semiconductor TFT and a second p-type oxide semiconductor TFT, both with top gate structures, where the gate insulating layers have a multilayer structure, allowing for different materials to be used for each type, and the source and drain electrodes are formed in the same layer, enabling efficient operation and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a CMOS structure is formed using conventional n-type and p-type semiconductors, then complementary logic functions can be achieved, but high power consumption and high operating voltages occur
Solution Approach 1:
The patent changes the material parameter from conventional semiconductors to oxide semiconductor materials, which inherently possess wide bandgap properties. This material parameter change enables both n-type and p-type TFTs to operate at lower voltages while maintaining stable characteristics, thereby reducing power consumption without sacrificing reliability
Solution Approach 2:
The patent employs composite oxide semiconductor structures with specific stacking configurations. The oxide semiconductor layers are combined with gate insulating layers and electrode layers to form a composite structure that optimizes both electrical performance and stability, achieving low-power operation with reliable TFT characteristics
2Reliability
If different gate insulating layer structures are used for n-type and p-type TFTs to optimize performance, then TFT characteristics improve, but manufacturing complexity and number of masks increase
Solution Approach 1:
The patent designs a universal gate insulating layer structure that serves both n-type and p-type TFTs. The same stacked configuration of gate insulating layers is used for both transistor types, allowing the structure to be formed in a single manufacturing process sequence. This universal design maintains optimal TFT characteristics while avoiding the need for separate processing steps for different transistor types
Solution Approach 2:
The patent merges the gate insulating layer formation processes for n-type and p-type TFTs into a single unified process. By combining what would traditionally be separate structures into one common configuration, the patent reduces the number of masks and processing steps required, thereby simplifying manufacturing while preserving the performance benefits of optimized gate insulation
3Manufacturing precision
If separate processing steps are used for n-type and p-type TFT fabrication, then manufacturing precision is maintained, but production time and cost increase
Solution Approach 1:
The patent combines the fabrication processes for n-type and p-type TFTs into a single integrated manufacturing sequence. The same processing steps, including oxide semiconductor film formation, gate insulating layer deposition, and electrode patterning, are performed simultaneously for both transistor types using common masks and process conditions, thereby maintaining precision while doubling productivity
Solution Approach 2:
The patent performs preliminary formation of oxide semiconductor films and gate insulating layers that will serve both n-type and p-type TFTs before subsequent differentiation steps. By preparing common structural elements in advance that can serve dual purposes, the patent reduces the total number of processing steps required while ensuring consistent manufacturing precision across both transistor types
Data Source
AI summary
A semiconductor device includes a first TFT of a first conductivity type and a second TFT of a second conductivity type. The first TFT includes a first semiconductor layer made of an oxide semiconductor material of the first conductivity type, a first gate insulating layer provided on the first semiconductor layer, a first gate electrode located opposite to a channel region of the first semiconductor layer with the first gate insulating layer interposed therebetween, and a first source electrode. The second TFT includes a second semiconductor layer made of an oxide semiconductor material of the second conductivity type or a transparent semiconductor material of the second conductivity type, a second gate insulating layer provided on the second semiconductor layer, a second gate electrode located opposite to a channel region of the second semiconductor layer with the second gate insulating layer interposed therebetween, and a second source electrode. The first gate insulating layer includes a first layer and a second layer provided on the first layer. The second layer of the first gate insulating layer and the second gate insulating layer are provided in the same layer.