Oxide-Semiconductor Current DAC for Compact 5G RF Circuits
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Solution Overview
Problem
High-frequency semiconductor devices, particularly those used in 5G communication systems, face challenges in miniaturization, power consumption reduction, and accuracy maintenance due to the increasing complexity and power requirements of high-frequency circuits, especially in digital-to-analog converter (DAC) components.
Innovation Solution
The semiconductor device incorporates constant current circuits with transistors using oxide semiconductors in the channel formation region, along with a buffer circuit and load transistors, to efficiently manage digital signals and reduce power consumption by allowing for impedance correction and miniaturization without compromising accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistors (same conductivity type with compound semiconductor like GaN) are used for high-frequency circuits, then high voltage resistance is achieved, but circuit area increases and power consumption increases
Solution Approach 1:
The patent merges the high voltage resistance function (traditionally requiring compound semiconductor transistors) with the miniaturization and low power consumption requirements by integrating multiple functions into a single transistor structure using oxide semiconductor materials, thereby reducing overall circuit area while maintaining reliability
Solution Approach 2:
The patent changes the material parameter from conventional compound semiconductors to oxide semiconductors, which enables both high voltage resistance and reduced power consumption simultaneously, resolving the contradiction between reliability and power efficiency
2Speed
If decode-type, binary-type, or segment-type DAC configurations are used for high-speed operation, then conversion speed is improved, but circuit area increases
Solution Approach 1:
The patent segments the DAC functionality into multiple constant current circuits that operate in parallel, where each circuit handles a portion of the conversion task. This segmentation enables high-speed operation while reducing the area per circuit compared to conventional unified DAC structures
Solution Approach 2:
The patent transitions from a planar DAC layout to a three-dimensional stacked configuration where constant current circuits are arranged in multiple layers, effectively utilizing vertical space to reduce the footprint area while maintaining high conversion speed through parallel processing
3Use of energy by stationary object
If DAC is placed close to analog front end for power saving, then power consumption is reduced, but impedance correction accuracy decreases
Solution Approach 1:
The patent introduces a buffer circuit as an intermediary between the DAC and the analog front end. This buffer circuit acts as a mediator that preserves signal integrity and impedance correction accuracy even when the DAC is positioned close to the analog front end, thereby enabling power saving without sacrificing precision
4Measurement precision
If circuit complexity increases to maintain accuracy in 5G communication, then communication performance is improved, but power consumption increases
Solution Approach 1:
The patent replaces conventional transistor-based circuit elements with oxide semiconductor transistors that inherently provide lower leakage current and higher efficiency. This substitution maintains communication accuracy through improved device characteristics while significantly reducing power consumption, eliminating the need for additional power-consuming complexity management circuits
Data Source
AI summary
To provide a semiconductor device with a novel structure. The semiconductor device includes a plurality of constant current circuits each given a digital signal. The constant current circuits each include a first transistor to a third transistor. The first transistor has a function of making a first current corresponding to set analog potential flow therethrough. The second transistor has a function of controlling the first current flowing between a source and a drain of the first transistor, in response to the digital signal. The third transistor has a function of holding the analog potential supplied to a gate of the first transistor, by being turned off. The first transistor to the third transistor each include a semiconductor layer including an oxide semiconductor in a channel formation region.