Silicon Oxide Doping Profile for Low-Voltage Resistive Memory
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Solution Overview
Problem
Current memory devices using magnetoresistance effect elements face challenges in optimizing dopant concentration distribution for efficient switching between low-resistance and high-resistance states, leading to higher power consumption and suboptimal performance.
Innovation Solution
A method of manufacturing memory devices involving ion implantation of dopants into silicon oxide followed by ion beam etching to achieve a specific dopant concentration distribution in the variable resistance material, ensuring higher dopant concentration at the top surface and lower at the bottom, which reduces the threshold and forming voltages, thereby enhancing switching efficiency and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dopant is introduced into silicon oxide by ion implantation with conventional concentration distribution, then the memory device can store data, but the threshold voltage and forming voltage are high leading to high power consumption
Solution Approach 1:
The patent applies local quality by creating a non-uniform dopant concentration distribution within the silicon oxide layer. Specifically, the dopant concentration is designed to be higher near the top surface (interface with variable resistance material) and lower near the bottom surface. This spatial variation in dopant concentration optimizes the local electrical properties: the higher concentration region near the top facilitates easier switching by reducing the threshold voltage, while the overall dopant profile maintains sufficient forming voltage for stable data storage, thereby reducing power consumption without sacrificing reliability
Solution Approach 2:
The patent employs parameter changes by systematically varying the dopant concentration as a function of depth within the silicon oxide layer. Through ion implantation with controlled energy and dose, the dopant concentration profile is engineered to transition from high at the top interface to low at the bottom interface. This parameter optimization directly addresses the contradiction by tuning the electrical characteristics (threshold voltage and forming voltage) to achieve both low power consumption and high switching efficiency
2Ease of manufacture
If uniform dopant concentration is used in silicon oxide, then the manufacturing process is simple, but the switching efficiency is suboptimal and power consumption is high
Solution Approach 1:
The patent implements local quality through controlled ion implantation that creates a depth-dependent dopant concentration profile. The implantation process uses specific energy levels and doses to ensure higher dopant concentration at the top surface region and lower concentration at the bottom region. This localized variation in dopant distribution optimizes switching efficiency and reduces power consumption while maintaining manufacturing feasibility through standard ion implantation equipment and processes
Solution Approach 2:
The patent applies preliminary action by pre-establishing the optimal dopant concentration profile during the ion implantation step itself, rather than requiring subsequent complex processing. The ion implantation parameters (energy, dose, angle) are carefully selected in advance to achieve the desired non-uniform distribution directly, simplifying the overall manufacturing process while enabling the performance benefits of non-uniform dopant distribution
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in memory devices with improved performance by lowering the threshold and forming voltages, enabling efficient data storage with reduced power consumption compared to reference memory cells.
Implementation Method 1
introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation
Implementation Method 2
etching the first surface of the silicon oxide with an ion beam
Data Source
AI summary
According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.