Oxide-in-Fin Channel Separation for Monolithic Stacked Transistors
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Solution Overview
Problem
Current methods for manufacturing stacked transistors face challenges such as defects due to lattice constant differences in epitaxially grown SiGe layers and increased costs associated with using silicon on insulator (SOI) wafers.
Innovation Solution
The use of localized oxidation techniques to form oxide layers within fins, separating top and bottom channels, which reduces parasitic capacitance and eliminates the need for sacrificial layers or expensive SOI wafers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If epitaxially grown SiGe layers are used to separate top and bottom channels, then transistor density is improved, but defects occur due to lattice constant differences
Solution Approach 1:
The patent extracts and removes the problematic SiGe sacrificial layer after it has served its purpose of defining the channel separation region. By taking out the layer that causes lattice mismatch defects, the invention eliminates the reliability issue while maintaining the beneficial channel separation geometry that improves transistor density.
Solution Approach 2:
The SiGe layer is used as a temporary, disposable sacrificial material during fabrication. It serves its function of defining the oxide formation region and is then completely removed. This approach allows the use of a material that would otherwise cause defects, but only temporarily, resolving the contradiction between achieving precise channel separation and avoiding lattice mismatch defects in the final device.
2Reliability
If silicon on insulator (SOI) wafers are used to form oxide layers, then electrostatic control is improved, but manufacturing cost increases
Solution Approach 1:
Instead of using expensive SOI wafers with global oxide layers, the patent applies oxidation locally only to the specific regions where channel separation is needed. This is achieved through selective catalytic oxidant deposition on the fin surfaces, creating oxide layers only where required rather than across the entire wafer, thereby reducing material costs while maintaining electrostatic control performance.
Solution Approach 2:
The patent introduces a catalytic oxidant material as an intermediary substance that enables selective oxide formation. This mediator allows oxidation to occur only in contact with the catalytic material, providing precise spatial control over oxide layer formation and eliminating the need for expensive SOI substrates while achieving the desired electrostatic control.
3Ease of manufacture
If localized oxidation techniques are used to form oxide layers, then manufacturing cost is reduced, but process complexity increases
Solution Approach 1:
The patent replaces traditional mechanical or lithographic patterning methods with a chemical field-based approach using catalytic oxidation. The catalytic oxidant material creates a chemical field that directs oxide formation automatically where the catalyst contacts the fin surface, eliminating the need for complex lithography steps and reducing overall process complexity despite the introduction of new chemical processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor density and performance by reducing defects and costs, while also improving electrostatic control and carrier mobility.
Implementation Method 1
annealing the deposited catalytic oxidant material to form an oxide in at least a portion of a volume of the fin
Implementation Method 2
annealing the deposited catalytic oxidant material to form an oxide in at least a portion of a volume of the fin
Data Source
AI summary
Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.