Oxide Semiconductor Flash Memory Channel for Uniform 3D Erase
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Solution Overview
Problem
Flash memory devices with a 3D structure using polysilicon channels face reduced carrier mobility and non-uniform electrical characteristics due to the use of polysilicon, and oxide semiconductor materials have low minority carrier concentration and mobility, making erase operations inefficient.
Innovation Solution
A flash memory device design incorporating a first gate electrode with a semiconductor material, a tunnel insulating pattern, a charge trapping pattern, a blocking pattern, and a channel made of an oxide semiconductor material, along with a second gate electrode, allows for effective program and erase operations by applying specific voltages to trap electrons and holes in the charge trapping pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If polysilicon is used for the channel in a 3D flash memory device, then the device can store large amounts of data, but carrier mobility decreases and electrical characteristics become non-uniform
Solution Approach 1:
The patent changes the material parameter of the channel from polysilicon to oxide semiconductor material, which fundamentally alters the electrical characteristics. This material substitution resolves the contradiction by providing both high carrier mobility and uniform electrical characteristics while maintaining the 3D structure's data storage capacity
Solution Approach 2:
The patent employs a composite structure combining oxide semiconductor material for the channel with specific gate electrode configurations. This composite approach enables simultaneous achievement of high carrier mobility in the channel and effective charge trapping, resolving the electrical characteristic uniformity issue while preserving large data storage capacity
2Reliability
If oxide semiconductor material is used for the channel, then carrier mobility improves, but erase operation becomes difficult due to low minority carrier concentration
Solution Approach 1:
The patent introduces a charge trapping pattern as an intermediary between the oxide semiconductor channel and the gate electrode. This intermediary layer enables effective charge storage and facilitates erase operations by allowing hole injection into the trapped electrons, thereby resolving the erase operation difficulty while preserving the high carrier mobility of the oxide semiconductor channel
Solution Approach 2:
The patent applies different materials and structures to different regions: the channel uses oxide semiconductor for high mobility, while the charge trapping pattern uses specific materials optimized for charge storage. This local differentiation resolves the contradiction by optimizing each region for its specific function - the channel for electron transport and the trapping pattern for charge storage and erase facilitation
3Device complexity
If a single gate electrode structure is used, then device complexity is reduced, but program and erase operations cannot be effectively controlled
Solution Approach 1:
The patent segments the gate electrode into multiple distinct components: a first gate electrode for program operation and a second gate electrode for erase operation. This segmentation enables independent control of program and erase functions, effectively resolving the control issue while maintaining manageable device complexity through modular architecture
Solution Approach 2:
The patent designs a multi-functional gate electrode system where the first gate electrode handles program operations and the second gate electrode handles erase operations. This universal design enables a single integrated structure to perform multiple distinct functions, resolving the operational control issue without proportionally increasing device complexity
Data Source
AI summary
Provided is a flash memory device including a first gate electrode including a semiconductor material, a tunnel insulating pattern in contact with an upper surface of the first gate electrode, a charge trapping pattern on the tunnel insulating pattern, a blocking pattern on the charge trapping pattern, a channel on the blocking pattern, the channel including an oxide semiconductor material, source/drain patterns on the channel, the source/drain patterns being spaced apart from each other, and a second gate electrode in contact with the channel, the second gate electrode being between adjacent source/drain patterns of the source/drain patterns.