Oxide Semiconductor FRAM Voltage Segmentation
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Solution Overview
Problem
Conventional ferroelectric random access memory (FRAM) designs face challenges with excessive write voltage damaging transistor devices due to the need for high voltage application through bit lines or word lines, and they are not suitable for high storage capacity and size scaling.
Innovation Solution
The proposed oxide semiconductor-based FRAM structure features a capacitor positioned under the channel of an oxide semiconductor field effect transistor, with a write electrode added to control write operations, reducing the risk of transistor damage by dividing the write voltage through bit lines and word lines, thereby reducing the layout area required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write voltage is applied through bit lines or word lines in conventional FRAM, then write operation is achieved, but transistor device is damaged due to excessive voltage
Solution Approach 1:
The write voltage application path is segmented into two independent paths: one through the bit line to the capacitor plate, and another through the word line to the gate. This segmentation allows the write voltage to be distributed and controlled separately, preventing excessive voltage from damaging the transistor channel while still achieving the necessary write operation.
Solution Approach 2:
The gate serves as an intermediary element that receives write voltage through the word line and transfers it to the capacitor plate. This intermediary mechanism allows the write operation to be performed without directly applying high voltage through the transistor channel, thereby protecting the transistor from damage while maintaining write functionality.
2Reliability
If conventional FeFET or FeRAM structures are used, then FRAM functionality is achieved, but layout area is large
Solution Approach 1:
The invention merges the capacitor and transistor gate into a shared structure where the capacitor plate is formed over the transistor gate. This merging eliminates the need for separate capacitor structures, significantly reducing the overall memory cell layout area while maintaining full FRAM functionality through the novel write voltage application mechanism.
Solution Approach 2:
The capacitor is positioned in a vertical dimension above the transistor gate rather than in the planar layout plane. This dimensional change allows the capacitor and transistor to share the same footprint area, reducing the overall memory cell size while maintaining functionality through three-dimensional integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the risk of transistor damage and allows for a more compact memory layout, enabling higher storage density and scalability while maintaining low power consumption and high-speed write/read capabilities.
Implementation Method 1
a ferroelectric dielectric layer on the write electrode
Implementation Method 2
an oxide semiconductor layer on the ferroelectric dielectric layer
Data Source
AI summary
An oxide semiconductor-based FRAM is provided in the present invention, including a substrate, a word line on the substrate, a gate insulating layer on the word line, an oxide semiconductor layer on the gate insulating layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain further connect respectively to a plate line and a bit line, a ferroelectric dielectric layer on the source, the drain and the oxide semiconductor layer, and a write electrode on the ferroelectric dielectric layer, wherein the write electrode, the ferroelectric dielectric layer, the oxide semiconductor layer, the gate insulating layer and the word line overlap each other in a direction vertical to the substrate.