Oxide Semiconductor GAA Gate Structure for Mobility and Junction Control
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Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the increasing complexity and difficulty of fabrication processes as feature sizes continue to decrease, necessitating improved methods for patterning and doping in semiconductor manufacturing.
Innovation Solution
The use of gate all-around (GAA) transistor structures, which are patterned using photolithography and self-aligned processes, combined with oxygen scavenging and barrier layers to enhance carrier mobility and reduce scattering, and the application of selective isotropic dry etching for precise doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are decreased to increase functional density, then production efficiency and cost are improved, but fabrication process difficulty increases
Solution Approach 1:
The fabrication process is divided into multiple self-aligned steps including forming first and second sacrificial layers at different heights, selective etching, and sequential doping. This segmentation allows each step to be optimized independently while maintaining overall process feasibility at reduced feature sizes
Solution Approach 2:
Sacrificial layers are formed and patterned in advance before the actual transistor structure is created. These preliminary sacrificial structures guide subsequent self-aligned doping and material deposition, enabling precise feature formation without requiring complex real-time alignment at each step
2Manufacturing precision
If conventional doping methods are used, then doping is achieved, but dopant diffusion causes poor junction definition and increased scattering
Solution Approach 1:
Ion implantation doping is performed before the barrier layer is formed, establishing precisely defined dopant profiles and junction locations. This preliminary doping action occurs when the channel structure is accessible, allowing accurate dopant placement without subsequent diffusion that would blur junction definitions
Solution Approach 2:
An oxide semiconductor barrier layer is introduced as an intermediary between the dopant source and the channel region. This barrier layer prevents unwanted dopant diffusion while allowing the desired dopant distribution to be established, thereby maintaining sharp junction definitions and reducing scattering
3Reliability
If carrier mobility is increased to improve device performance, then ON current increases, but scattering effects become more significant
Solution Approach 1:
The oxide semiconductor barrier layer serves as a mediator that filters and controls the interaction between dopants and the channel. It allows beneficial dopant effects to enhance carrier mobility while blocking sources of Coulomb scattering and reducing surface roughness effects at the interface
Solution Approach 2:
The material composition and structural parameters of the barrier layer are optimized to achieve the right balance between allowing carrier transport and filtering scattering mechanisms. By controlling the barrier layer's properties, carrier mobility is enhanced while scattering is suppressed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by increasing carrier mobility and ON current while reducing Coulomb and surface roughness scattering, leading to more reliable and efficient semiconductor devices.
Implementation Method 1
a gate structure wrapping around a channel region of each of the oxide semiconductor channel layers
Implementation Method 2
improves device performance by increasing carrier mobility and ON current while reducing Coulomb and surface roughness scattering
Data Source
AI summary
A semiconductor device includes a substrate. An oxide semiconductor channel layer is over the substrate. A gate structure is over the oxide semiconductor channel layer. The gate structure includes an oxide semiconductor barrier layer over the oxide semiconductor channel layer, a gate dielectric layer over the oxide semiconductor barrier layer, and a gate metal over the gate dielectric layer. Source/drain electrodes are in contact with opposite ends of the oxide semiconductor channel layer.