Oxide Semiconductor Gate Insulation for Hydrogen Blocking
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Solution Overview
Problem
Semiconductor devices using oxide semiconductors face challenges in preventing hydrogen from entering the channel region, which affects the threshold voltage and manufacturing yield, while using an oxide layer with excessive oxygen reduces reliability by acting as an electron-trap.
Innovation Solution
A semiconductor device is designed with specific regions having varying thicknesses of the gate insulating layer and impurity concentrations, including a hydrogen-trapping region in the oxide and gate insulating layers to prevent hydrogen from reaching the channel region, while allowing hydrogen supply to the source and drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If an oxide layer containing excessive oxygen is used as an insulating layer to suppress hydrogen from entering the channel region, then hydrogen suppression is improved, but reliability deteriorates due to electron-trapping
Solution Approach 1:
The gate insulating layer is divided into a first region (overlapping the gate electrode) with thickness of 200 nm or more and second/third regions (not overlapping the gate electrode) with thickness of 150 nm or less. This segmentation allows the first region to suppress hydrogen entry while the thinner second/third regions reduce electron-trapping effects, resolving the contradiction between hydrogen suppression and reliability.
Solution Approach 2:
Different regions of the gate insulating layer are given different thicknesses to perform different functions: the first region (thicker) provides hydrogen suppression in the channel area, while the second and third regions (thinner) minimize electron-trapping in source/drain areas. This local differentiation resolves the contradiction by optimizing each region's properties for its specific function.
2Object-affected harmful factors
If the gate insulating layer thickness is increased to suppress hydrogen, then hydrogen suppression is improved, but manufacturing precision requirements increase due to varying thickness specifications
Solution Approach 1:
The gate insulating layer is segmented into multiple regions with different thickness specifications (200 nm or more in the first region, 150 nm or less in the second and third regions). This segmentation allows hydrogen suppression where needed while reducing electron-trapping in other areas, and the thickness values are set within controllable ranges for manufacturing.
Solution Approach 2:
The thickness parameter of the gate insulating layer is changed across different regions to optimize both hydrogen suppression and electron-trapping prevention. By specifying different thickness ranges for different regions, the invention achieves the desired functionality while maintaining manufacturability through clear parameter definitions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses hydrogen entry into the channel region, improving the reliability and yield of the semiconductor device by maintaining low resistance in the source and drain regions.
Implementation Method 1
the gate insulating layer covering the oxide semiconductor layer... a thickness of the gate insulating layer in the first region is 200 nm or more... the thickness of the gate insulating layer in the second region and the third region is 150 nm or less
Implementation Method 2
an amount of impurities contained in the oxide semiconductor layer in the second region is greater than an amount of impurities contained in the oxide semiconductor layer in the first region
Data Source
AI summary
A method for manufacturing semiconductor device according to an embodiment includes: forming an oxide semiconductor layer above a substrate; forming a gate insulating layer above the oxide semiconductor layer; forming a metal oxide layer containing aluminum as a main component above the gate insulating layer; performing a heat treatment in a state where the metal oxide layer is formed above the gate insulating layer; removing the metal oxide layer after the heat treatment; and forming a gate electrode above the gate insulating layer.