Polycrystalline Oxide Semiconductor Gate Layout to Prevent Shorts
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Solution Overview
Problem
Semiconductor devices using oxide semiconductors with polycrystalline structures face challenges in achieving high reliability while maintaining high field effect mobility and preventing inter-electrode short circuits.
Innovation Solution
The semiconductor device incorporates a first gate electrode, a scan line, an oxide semiconductor layer with a polycrystalline structure, source and drain electrodes, and a second gate electrode that overlaps the oxide semiconductor layer but is spaced from the source and drain electrodes, ensuring electrical connection through a connection electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a second gate electrode is added to overlap the oxide semiconductor layer, then field effect mobility is improved, but device complexity increases
Solution Approach 1:
The gate structure is segmented into a first gate electrode and a second gate electrode that are electrically connected but spatially separated. The first gate electrode is positioned over the oxide semiconductor layer while the second gate electrode is spaced from the source and drain electrodes, dividing the gate function into multiple components to achieve high field effect mobility while managing structural complexity
Solution Approach 2:
An insulating layer with a first opening portion is introduced as an intermediary between the first and second gate electrodes. This opening portion allows electrical connection between the two gate electrodes while maintaining their spatial separation, enabling the dual-gate structure to function as a unified gate system without direct physical contact between the gate electrodes themselves
2Reliability
If the second gate electrode is positioned to overlap the oxide semiconductor layer, then device performance is improved, but risk of inter-electrode short circuit increases
Solution Approach 1:
The second gate electrode is extracted from direct overlap with the source and drain electrodes, positioning it only over the oxide semiconductor layer with explicit spacing from the electrodes. This separation removes the harmful proximity that could lead to short circuits while preserving the beneficial overlap with the oxide semiconductor layer for enhanced device performance
Solution Approach 2:
The insulating layer is positioned beforehand between the second gate electrode and the source/drain electrodes, creating a protective cushion that prevents potential short circuits. This insulating barrier is established in advance to cushion against any harmful electrical interaction between the gate structure and the source/drain electrodes
Data Source
AI summary
A semiconductor device includes a first gate electrode, an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure over the first gate electrode, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, and a second gate electrode overlapping the first gate electrode and the oxide semiconductor layer over the source electrode and the drain electrode. In a plan view, the second gate electrode is located with a space from each of the source electrode and the drain electrode. The second gate electrode is electrically connected to the first gate electrode.