Oxide Semiconductor Gate Layout for Stable, Compact Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of transistor circuits in semiconductor and display devices using oxide semiconductors is hindered by defects on the back channel side of the oxide semiconductor layer, which can lead to variations in transistor operation and require additional structures like back gate electrodes, interfering with circuit miniaturization and pixel circuit size.
Innovation Solution
A semiconductor device design that includes a first gate electrode, a first oxide semiconductor layer, source and drain electrodes, a second gate insulating layer, a second oxide semiconductor layer, and a second gate electrode, where the second gate electrode is in contact with the second oxide semiconductor layer, and a connecting electrode electrically connects the first and second gate electrodes, allowing for reduced area requirements and miniaturization by overlapping components in a planar view.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a back gate electrode is arranged via an insulating layer above the oxide semiconductor layer to suppress defects on the back channel side, then transistor operation stability is improved, but device complexity increases due to additional individual wiring and circuit requirements
Solution Approach 1:
The patent connects the bottom gate electrode and back gate electrode to the same potential by electrically connecting them, merging their functions into a single gate structure. This eliminates the need for separate wiring and control circuits for the back gate, reducing device complexity while maintaining the stability benefits of having a back gate to suppress defects on the back channel side of the oxide semiconductor layer
2Reliability
If contact structures are arranged to connect bottom gate electrode and back gate electrode to a region different from the back gate electrode, then transistor characteristics are stabilized, but area for circuit miniaturization is reduced
Solution Approach 1:
The patent merges the bottom gate electrode and back gate electrode into a single integrated gate structure with unified wiring, eliminating the need for separate contact structures in different regions. This reduces the area required for circuit miniaturization while maintaining stable transistor characteristics through the coordinated gate structure
3Ease of operation
If a capacity element is formed using conductive layers to store charge for pixel circuit operation, then pixel circuit functionality is achieved, but area for pixel circuit miniaturization is reduced
Solution Approach 1:
The patent makes the gate electrode structure serve multiple functions: it acts as both the control gate for the transistor and as one electrode of the capacity element (storage capacitor) for the pixel circuit. The gate insulating layer serves as the dielectric for the capacity element. This multi-functionality eliminates the need for separate capacity element structures, reducing pixel circuit area while maintaining full functionality
Data Source
AI summary
A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.