Oxide Semiconductor Gate Structure for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor elements leads to increased parasitic capacitance, which reduces the responsiveness of transistors and semiconductor devices, making it difficult to control manufacturing steps and resulting in variations in transistor characteristics and reliability.
Innovation Solution
A semiconductor device structure is developed with a gate electrode layer having regions of different widths and taper angles, and an oxide semiconductor layer with reduced oxygen vacancies, along with a manufacturing method that includes specific etching and planarization treatments to minimize parasitic capacitance and interface states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor elements are miniaturized to improve integration density, then productivity and device functionality are improved, but parasitic capacitance increases which reduces transistor responsiveness and reliability
Solution Approach 1:
The patent introduces a three-dimensional gate structure where the gate electrode extends in multiple dimensions (planar region and side surface region), transforming the traditional two-dimensional gate configuration. This dimensional change allows the gate to control the channel more effectively while reducing parasitic capacitance between the gate and source/drain electrodes, thereby maintaining transistor responsiveness despite miniaturization.
Solution Approach 2:
The gate electrode is segmented into distinct regions: a planar gate region and a side surface gate region. This segmentation allows each region to perform specific functions - the planar region provides primary gate control while the side surface region reduces parasitic capacitance and improves channel control, collectively enhancing transistor performance in miniaturized devices.
2Productivity
If transistor dimensions are reduced to improve integration density, then productivity is improved, but manufacturing control difficulty increases leading to variations in transistor characteristics
Solution Approach 1:
The patent applies different structural characteristics to different regions of the gate electrode. The planar gate region has a specific width and thickness optimized for gate control, while the side surface gate region extends vertically to provide enhanced control at the channel edges. This local differentiation allows each region to be optimized for its specific function, improving overall manufacturing uniformity and reducing characteristic variations.
3Device complexity
If conventional gate structures are used in miniaturized transistors, then device complexity is low, but parasitic capacitance increases reducing device performance
Solution Approach 1:
The gate electrode is extended into the vertical dimension with a side surface gate region that contacts the channel from the side. This three-dimensional configuration reduces the overlap area between the gate and source/drain electrodes, thereby reducing parasitic capacitance while maintaining a relatively simple fabrication process that builds upon conventional planar gate structures.
Data Source
AI summary
A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.