Oxide Semiconductor Gate Stack Layout for Compact Stable Transistors
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Solution Overview
Problem
The miniaturization of transistor circuits is hindered by the need for separate regions for contact structures and capacitance elements in semiconductor devices using oxide semiconductor layers, which increases complexity and interferes with circuit miniaturization.
Innovation Solution
A semiconductor device configuration that includes a first gate electrode, a first oxide semiconductor layer, and a second gate electrode in contact with the second oxide semiconductor layer, with a connecting electrode electrically connecting the first and second gate electrodes through an aperture, allowing for reduced area requirements and simplified structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate contact structures and capacitance elements are arranged in different regions, then transistor characteristics are stabilized, but circuit miniaturization is interfered with
Solution Approach 1:
The patent combines the contact structure and capacitance element into a single integrated structure. The capacitance element is formed using the same conductive layers and insulating layers as the contact structure, eliminating the need for separate regions. This merging approach maintains the electrical connection function while simultaneously providing the capacitance function, thus stabilizing transistor characteristics without increasing circuit area.
Solution Approach 2:
The conductive layers and insulating layers in the invention serve multiple functions simultaneously. The same conductive layer forms both the contact electrode and one electrode of the capacitance element, while the insulating layer serves as both the gate insulating layer and the capacitor dielectric. This multi-functionality allows the structure to provide both contact and capacitance functions within the same region, enabling circuit miniaturization while maintaining transistor stability.
2Reliability
If capacitance elements are formed with separate electrodes, then required capacitance is achieved, but pixel circuit miniaturization is interfered with
Solution Approach 1:
The patent merges the capacitance element electrodes with the gate electrode and source/drain electrodes. The gate electrode serves dual purposes as both the transistor gate and one electrode of the capacitance element. This integration eliminates the need for separate capacitance electrodes, significantly reducing the area required for pixel circuits while maintaining the necessary capacitance function for stable operation.
Solution Approach 2:
The invention utilizes the vertical stacking of layers to achieve capacitance without increasing planar area. By forming the capacitance element in the vertical dimension using stacked conductive and insulating layers, the patent achieves the required capacitance while minimizing the horizontal footprint of the pixel circuit, thus enabling effective miniaturization.
3Reliability
If back gate electrode is arranged via insulating layer above oxide semiconductor layer, then transistor characteristics are stabilized, but device complexity increases
Solution Approach 1:
The patent combines the back gate electrode function with the existing gate electrode structure. Instead of adding a separate back gate electrode above the oxide semiconductor layer, the invention utilizes the gate electrode and source/drain electrodes to simultaneously serve as capacitance electrodes. This merging approach stabilizes transistor characteristics without increasing structural complexity or requiring additional manufacturing steps.
Data Source
AI summary
A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.