Oxide Semiconductor Gate Stack for Threshold Voltage Stability
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Solution Overview
Problem
Semiconductor devices using oxide semiconductors for channels face variations in electrical characteristics due to electron or hole trapping in insulating layers, particularly under negative voltage stress and light irradiation, leading to shifts in electrical characteristics.
Innovation Solution
A semiconductor device configuration with specific thickness ranges for gate insulating layers containing silicon and nitrogen, silicon and oxygen, and aluminum and oxygen, along with a metal oxide layer containing aluminum, is employed to improve reliability by controlling the trapping of holes and electrons, thereby stabilizing electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional insulating layer structure is used in oxide semiconductor devices, then the device can be formed with a simple structure and low-temperature process, but the electrical characteristics vary due to electron or hole trapping under stress test and light irradiation
Solution Approach 1:
The insulating layer is divided into multiple sub-layers with different compositions and functions. The gate insulating layer includes a first insulating layer (silicon nitride or silicon oxynitride) and a second insulating layer (silicon oxide), each with specific thickness ranges. This segmentation allows each layer to address different aspects of the problem: the first layer provides barrier properties to prevent impurity diffusion, while the second layer provides oxygen supply to reduce oxygen vacancies in the oxide semiconductor layer, thereby resolving the contradiction between simple structure and reliability.
Solution Approach 2:
The gate insulating layer uses a composite structure combining silicon nitride/silicon oxynitride and silicon oxide materials. This composite approach leverages the complementary properties of each material: silicon nitride provides excellent barrier properties against impurity diffusion, while silicon oxide provides oxygen supply capabilities. The combination achieves both manufacturing simplicity and improved electrical characteristic stability under stress conditions.
2Reliability
If the insulating layer thickness is increased to prevent electron or hole trapping, then electrical characteristic stability improves, but the device structure becomes more complex and manufacturing难度 increases
Solution Approach 1:
The patent specifies precise thickness parameters for each insulating layer: the first insulating layer is 50-200 nm and the second insulating layer is 50-200 nm, with their total being 100-400 nm. These parameter optimizations ensure that the layers are thick enough to provide adequate barrier and oxygen supply functions, yet thin enough to maintain manufacturing simplicity and avoid excessive complexity. The aluminum oxide layer thickness of 1-20 nm further optimizes the balance between protection function and structural simplicity.
3Reliability
If a thick insulating layer is used to shield holes effectively, then electrical characteristic stability under negative voltage stress improves, but the manufacturing process becomes more difficult and time-consuming
Solution Approach 1:
The patent applies local quality by positioning the aluminum oxide layer specifically at the interface between the gate insulating layer and the oxide semiconductor layer, where hole trapping is most problematic. This localized placement provides targeted hole shielding exactly where needed, rather than uniformly increasing the thickness of the entire insulating structure. The specific thickness of 1-20 nm for the aluminum oxide layer ensures adequate hole blocking while maintaining manufacturing efficiency.
Data Source
AI summary
A semiconductor device according to an embodiment includes: a first gate electrode; a first insulating layer on the first gate electrode; an oxide semiconductor layer on the first insulating layer; a second insulating layer on the oxide semiconductor layer; and a second gate electrode on the second insulating layer. The first insulating layer includes a first layer including silicon and nitrogen, a second layer including silicon and oxygen, and a third layer including aluminum and oxygen. A thickness of the first layer is 10 nm or more and 190 nm or less. A thickness of the second layer is 10 nm or more and 100 nm or less. A total thickness of the first layer and the second layer is 200 nm or less. A thickness of the third layer 1 nm or more and 10 nm or less.