Semiconductor Oxide Grain Boundary Control for Carrier Flow
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Solution Overview
Problem
Current semiconductor oxides used in integrated assemblies, such as those comprising indium, gallium, and zinc, face challenges in optimizing carrier flow and grain boundary configurations to enhance performance and uniformity in transistors, particularly in memory arrays and other applications.
Innovation Solution
The development of semiconductor oxides with tailored grain boundaries and compositions, where carrier flow is either parallel to or crosses grain boundaries, allowing for adjustable carrier flow paths and uniformity across multiple access devices, achieved through specific deposition and annealing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor oxides with traditional compositions are used in transistors, then manufacturing process is simpler, but carrier flow performance and uniformity are insufficient
Solution Approach 1:
The patent applies local quality by creating specific grain boundary configurations within the semiconductor oxide channel material. Different regions of the channel material have different grain boundary characteristics, with some regions having grain boundaries parallel to carrier flow and others having grain boundaries that cross the flow path. This localized variation in grain boundary structure optimizes carrier flow performance in different areas of the transistor channel.
Solution Approach 2:
The patent changes physical and chemical parameters of the semiconductor oxide material, specifically controlling grain size, grain boundary orientation, and material composition (including oxygen content and metal ratios). By adjusting these parameters during deposition and annealing processes, the patent achieves improved carrier flow performance while managing the complexity of grain boundary configurations.
2Reliability
If grain boundaries are configured parallel to carrier flow, then carrier flow uniformity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by performing annealing treatments before final device fabrication to pre-establish the desired grain boundary configurations. The annealing process promotes grain growth and alignment in directions favorable for carrier flow uniformity, preparing the material structure in advance to reduce subsequent manufacturing precision requirements.
Solution Approach 2:
The patent utilizes phase transitions during annealing processes to reorganize the grain structure of the semiconductor oxide. By controlling temperature and atmosphere during annealing, the material undergoes phase transitions that promote grain growth and alignment, achieving the desired grain boundary configurations parallel to carrier flow paths.
3Reliability
If semiconductor oxide composition is optimized for performance, then transistor performance improves, but deposition process complexity increases
Solution Approach 1:
The patent employs composite materials by combining multiple metal oxides (such as indium oxide, gallium oxide, zinc oxide, and tin oxide) in specific ratios within the semiconductor channel material. This composite approach allows optimization of electrical properties, carrier flow, and grain boundary characteristics while managing deposition process complexity through established co-deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables tailored carrier flow and improved performance by modifying grain boundaries per unit length, enhancing specific applications and ensuring uniformity across identical access devices in memory arrays.
Implementation Method 1
The semiconductor oxide is deposited over a conductive material. The depositing is physical vapor depositing
Implementation Method 2
The deposited semiconductor oxide is annealed. The annealing forms a grain boundary within the semiconductor oxide
Data Source
AI summary
Some embodiments include an integrated assembly having a gate material, an insulative material adjacent the gate material, and a semiconductor oxide adjacent the insulative material. The semiconductor oxide has a channel region proximate the gate material and spaced from the gate material by the insulative material. An electric field along the gate material induces carrier flow within the channel region, with the carrier flow being along a first direction. The semiconductor oxide includes a grain boundary having a portion which extends along a second direction that crosses the first direction of the carrier flow. In some embodiments, the semiconductor oxide has a grain boundary which extends along the first direction and which is offset from the insulative material by an intervening portion of the semiconductor oxide. The carrier flow is within the intervening region and substantially parallel to the grain boundary. Some embodiments include methods of forming integrated assemblies.