Capacitorless Oxide Heterojunction Transistor Memory Cell
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices with a 2T/1C configuration require frequent refresh operations, leading to complex controller circuits and high power dissipation due to the need for capacitors with large capacitance, which increases the occupied area and decreases integration levels.
Innovation Solution
A semiconductor memory device utilizing an oxide heterojunction transistor with a 1T configuration, where the transistor functions as both a storage and control element, eliminating the need for a capacitor and allowing data storage through resistance state manipulation of the interfacial layer, reducing refresh frequency and power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is used in 2T/1C memory configuration to store data, then data retention is achieved, but the occupied area increases and integration level decreases
Solution Approach 1:
The patent extracts and removes the capacitor component from the memory cell structure, transitioning from a 2T/1C configuration to a capacitorless 1T configuration. The data storage function is achieved through the resistance state of the interfacial layer in the oxide heterojunction transistor rather than through capacitor charge storage, thereby eliminating the area occupied by the capacitor while maintaining data retention capability
Solution Approach 2:
The patent changes the fundamental parameter used for data storage from electrical charge (in capacitor) to resistance state (in interfacial layer). By utilizing the high resistance state and low resistance state of the interfacial layer formed at the oxide heterojunction, the memory device achieves non-volatile or low-power retention without requiring a capacitor, thus reducing the occupied area while maintaining reliability
2Reliability
If frequent refresh operations are performed in 2T/1C memory, then data retention is maintained, but power dissipation increases and controller circuit becomes complex
Solution Approach 1:
The patent removes the refresh operation mechanism from the memory system by eliminating the capacitor that requires periodic recharging. The oxide heterojunction transistor's interfacial layer maintains its resistance state without external intervention, thereby eliminating the power consumption associated with refresh operations while maintaining data retention
Solution Approach 2:
The interfacial layer in the oxide heterojunction transistor exhibits self-maintaining resistance states that do not require external refresh operations. The high resistance and low resistance states are inherently stable and can be maintained without continuous power supply or control circuit intervention, enabling the memory to serve itself and eliminate the complex controller circuit and power dissipation associated with refresh operations
3Duration of action of stationary object
If capacitor capacitance is increased to extend retention time, then data retention time increases, but occupied area increases and integration level decreases
Solution Approach 1:
The patent extracts the capacitor component entirely from the memory cell, replacing it with an oxide heterojunction transistor whose interfacial layer provides the retention function. This eliminates the need to increase capacitor capacitance to extend retention time, as the resistance-based storage mechanism inherently provides stable retention without area penalty
Solution Approach 2:
The patent changes the retention mechanism from capacitor charge retention (which requires large capacitance for long retention) to resistance state retention in the interfacial layer. The resistance states are inherently stable and can be maintained indefinitely or for extended periods without requiring increased component size, thus achieving long retention time without increasing occupied area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 1T configuration increases integration levels, simplifies the controller circuit, reduces power dissipation, and allows for long-term data storage without the need for refresh operations, thereby enhancing the memory device's performance and efficiency.
Implementation Method 1
an interfacial layer between the oxide substrate and the oxide film behaves like two-dimensional electron gas
Data Source
AI summary
A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device includes an oxide heterojunction transistor which includes: an oxide substrate; an oxide film on the oxide substrate, wherein an interfacial layer between the oxide substrate and the oxide film behaves like two-dimensional electron gas; a source electrode and a drain electrode being located on the oxide film and electrically connected with the interfacial layer; a front gate on the oxide film; and a back gate on a lower surface of the oxide substrate, wherein the source electrode and the drain electrode of the oxide heterojunction transistor are respectively connected with a first word line and a first bit line for reading operation, and wherein the front gate and the back gate are respectively connected with a second word line and a second bit line for writing operation.