Semiconductor Gate Stack Using Oxide Interposer for Defect Reduction
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Solution Overview
Problem
As semiconductor devices strive for increased integration density, challenges arise from managing Si/Ge intermixing and N-type Metal Gate (NMG) extrusion defects, which degrade device performance and reliability.
Innovation Solution
The use of a Disposable Oxide Interposer (DOI) process replaces silicon germanium with oxide materials like silicon dioxide or silicon oxynitride, allowing higher dopant concentrations and reducing intermixing, followed by selective etching to prevent NMG extrusion defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon germanium is used as dummy material, then manufacturing process is simplified, but Si/Ge intermixing occurs causing device performance degradation
Solution Approach 1:
An oxide interposer layer is introduced between the silicon channel and the silicon germanium dummy material. This intermediary layer prevents direct contact between silicon and germanium, thereby eliminating Si/Ge intermixing while maintaining the simplified manufacturing process benefits of using silicon germanium dummy material.
Solution Approach 2:
The oxide interposer is designed as a disposable temporary structure that facilitates the manufacturing process but is subsequently removed. This allows the use of silicon germanium dummy material during fabrication without permanently introducing intermixing issues in the final device.
2Reliability
If higher dopant concentrations are used, then channel resistance is reduced improving device performance, but NMG extrusion defects occur
Solution Approach 1:
The oxide interposer layer is formed in advance to counteract the harmful effect of NMG extrusion. By providing this protective barrier before high-dopant concentration processing, the interposer prevents dopant diffusion that would otherwise cause NMG extrusion defects, enabling higher dopant concentrations to be used safely.
Solution Approach 2:
The oxide interposer acts as a mediator between the high-dopant concentration environment and the metal gate structure. This intermediary layer allows high dopant concentrations to be introduced into the channel region while blocking the dopants from migrating to and causing extrusion of the metal gate.
3Productivity
If minimum feature size is reduced to increase integration density, then more components are integrated, but manufacturing precision and defect control become more difficult
Solution Approach 1:
The oxide interposer layer serves as a protective intermediary that enables precise control of dopant distribution in miniaturized structures. This intermediary facilitates accurate manufacturing even at reduced feature sizes by preventing unwanted dopant migration and intermixing that would otherwise be magnified at smaller dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by reducing channel resistance and improving electrical characteristics, such as lower resistance and higher drive currents, while preventing manufacturing defects.
Implementation Method 1
The DOI process replaces silicon germanium with an oxide material, which reduces the intermixing of silicon and germanium and eases the diffusion of germanium through the oxide/silicon interface
Implementation Method 2
The disclosed method allows for the introduction of higher concentrations of n-type dopants, such as phosphorus, arsenic, or antimony, into the source/drain regions of NFETs
Data Source
AI summary
In some implementations, a method may include forming a multi-layer stack over a substrate. The multi-layer stack has alternating layers of first semiconductor layers and second semiconductor layers. Additionally, the device may include removing the first semiconductor layers in a first region of the substrate. The device may also include forming a disposable material between the second semiconductor layers in the first region. Moreover, the device may include forming source/drain regions adjacent to the second semiconductor layers and the disposable material in the first region. Finally, the device may include replacing the disposable material in the first region with metal gate structures.