Oxide-Isolated Strained Channel Fin on Bulk Substrate
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Solution Overview
Problem
Current bulk FinFET fabrication processes face challenges such as mobility degradation, threshold voltage variations, random-dopant-fluctuation, and parasitic channel formation due to non-uniform doping and STI recess processes, which affect the accuracy of fin width and height, and lead to increased capacitance without a concomitant increase in drive current.
Innovation Solution
A novel fin structure with a bottom strain-relaxed buffer region, a central dielectric isolation region, and a top active region, where the central isolation region is formed by a selective anneal-driven reaction between germanium dioxide and silicon germanium, providing additional isolation and strain without relying on STI recess processes, thus avoiding dopant diffusion and parasitic channel formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If STI recess processes are used to define fin dimensions, then fin width and height can be controlled, but dopant diffusion and parasitic channel formation occur leading to mobility degradation and threshold voltage variations
Solution Approach 1:
The patent removes the STI recess process entirely from the fabrication sequence. Instead of using STI recess to define fin dimensions, the invention uses a selective epitaxial growth process where the fin structure is formed directly to the desired height through controlled silicon germanium and silicon layer deposition, eliminating the source of dopant diffusion and parasitic channel formation
Solution Approach 2:
The patent performs preliminary dimension definition through precise control of epitaxial growth parameters before any doping or gate formation steps. The fin width and height are established during the initial selective epitaxial growth of silicon germanium and silicon layers, ensuring that subsequent processing steps do not require STI recess and thus avoid associated reliability issues
2Adaptability or versatility
If non-uniform doping is applied to bulk FinFETs, then device characteristics can be adjusted, but random-dopant-fluctuation and mobility degradation occur
Solution Approach 1:
The patent implements local quality through a vertically stratified fin structure with distinct regions: a silicon germanium bottom region for strain induction, a dielectric middle region for isolation, and a silicon top region for active channel formation. This spatial differentiation allows localized functional optimization without relying on non-uniform doping, thereby avoiding random-dopant-fluctuation while maintaining device characteristic adaptability through material composition control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurately defined active fin heights and widths, reduces dopant diffusion, and minimizes parasitic channel formation, enhancing the reliability and performance of FinFET devices by maintaining strain and isolation throughout the fin channel.
Implementation Method 1
the central isolation region is formed by a selective anneal-driven reaction between germanium dioxide and silicon germanium
Implementation Method 2
the central isolation region is formed by a selective anneal-driven reaction between germanium dioxide and silicon germanium
Implementation Method 3
The use of silicon germanium in semiconductor devices such as FinFETs provides desirable device characteristics, including the introduction of strain at the interface between the silicon germanium of the active device and the underlying silicon substrate
Data Source
AI summary
Embodiments of the invention are directed to a semiconductor device that includes a substrate formed from a first type of semiconductor material, along with a fin formed on the substrate. The fin includes a fin channel region configured to include a bottom region, a central region, and a top active region. The central region includes a dielectric material and couples the bottom region to the top active region. The top active region includes a second type of semiconductor material, and the bottom region includes a third type of semiconductor material.