Multi-Layer Oxide Isolation Structure for Thermal Stress Management
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Solution Overview
Problem
The existing isolation layer structures in semiconductor memory devices suffer from dislocations and electrical characteristic deterioration due to thermal expansion and shrinkage, particularly in non-volatile memory devices with stacked structures, which affect the reliability and performance of these devices.
Innovation Solution
The implementation of a multi-layer oxide structure comprising first, second, third, and fourth oxide layer patterns with specific dimensions and properties, where the fourth oxide layer pattern has an expansion/shrinkage rate of less than 5% at 900 to 1000°C, and includes undoped silicate glass or HDP-CVD oxide, with voids to accommodate thermal stress, thereby improving structural stability and preventing dislocations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer insulative material is used to form the isolation layer, then the manufacturing process is simple, but thermal expansion and shrinkage during heat treatment cause dislocations and deteriorate electrical characteristics
Solution Approach 1:
The isolation layer is formed using a composite structure consisting of a first insulative material layer (e.g., silicon oxide) and a second insulative material layer (e.g., undoped silicate glass or HDP-CVD oxide) with different thermal expansion/shrinkage properties. This composite structure allows the layers to compensate for each other's thermal stress during heat treatment, preventing dislocations and maintaining electrical characteristics while still providing effective isolation.
2Reliability
If the trench width is increased to reduce stress, then dislocations are reduced, but the device area increases and manufacturing precision requirements change
Solution Approach 1:
The patent applies different insulative materials with specific thermal properties to different regions or layers within the isolation structure. The first insulative material layer and second insulative material layer are selectively formed with different composition ratios and thermal expansion characteristics, allowing localized stress management without increasing the overall trench dimensions.
3Manufacturing precision
If heat treatment temperature is increased to improve isolation layer formation, then the isolation layer quality improves, but thermal expansion causes more dislocations
Solution Approach 1:
The patent changes the material composition parameters of the insulative layers, specifically using a second insulative material layer with lower thermal expansion/shrinkage rate than the first layer. This parameter change allows the structure to withstand high heat treatment temperatures (900-1000°C) without excessive thermal stress, maintaining both isolation layer quality and preventing substrate dislocations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces dislocations and improves the structural stability of the semiconductor device by allowing the oxide layers to expand and shrink without causing substrate damage, maintaining electrical integrity and enhancing the reliability of non-volatile memory devices.
Implementation Method 1
the fourth oxide layer pattern may include an oxide having an expansion/shrinkage rate of less than about 5% at a temperature of about 900 to 1,000° C.
Implementation Method 2
the fourth oxide layer pattern may have a void therein... allowing the oxide layers to expand and shrink without causing substrate damage
Data Source
AI summary
An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein.