Oxide Layer Electrical Isolation for Fine Pitch Flip Chip Bonding

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Solution Overview

Problem

In fine pitch flip chip semiconductor packaging, existing technologies face challenges in forming reliable and robust solder joints between the flip chip and printed circuit board due to potential solder bridges between adjacent interconnect structures, leading to defects from misalignment or irregular bump diameters.

Innovation Solution

A method involving the formation of an oxide layer over signal traces on the substrate, which prevents electrical contact and maintains isolation between solder bumps and signal traces, allowing for closer interconnect spacing without bridging during the solder reflow process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If solder mask dam is used to prevent solder bridging, then solder joint reliability is improved, but lateral space is consumed limiting interconnect density

Engineering Contradiction:
Improvesolder joint reliabilityVSAvoidlateral space
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts the solder mask dam structure and replaces it with an oxide layer formed directly on the signal trace. This removes the need for lateral clearance between solder bumps and signal traces, as the oxide layer provides electrical isolation without consuming additional space. The extraction principle resolves the contradiction by eliminating the space-consuming solder mask dam while maintaining solder joint reliability through the oxide layer barrier.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the physical-chemical state of the signal trace surface by forming an oxide layer. This parameter change (from metallic to oxidized surface) provides electrical isolation that prevents solder bridging, thereby maintaining reliability without requiring additional lateral space. The parameter change transforms the signal trace surface properties to achieve both reliability and space efficiency.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If fine pitch bonding is implemented to increase interconnect density, then packaging cost is reduced, but solder bridging defects increase due to misalignment or irregular bump diameters

Engineering Contradiction:
Improveinterconnect densityVSAvoidsolder joint reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces an oxide layer as an intermediary barrier between the solder bump and the signal trace. This intermediary layer provides a safety margin that prevents electrical bridging even when solder bumps are misaligned or have irregular diameters in fine pitch applications. The mediator principle resolves the contradiction by enabling high interconnect density while maintaining reliability through the protective oxide barrier.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies beforehand cushioning by forming an oxide layer on the signal trace prior to solder bump attachment. This pre-established protective layer cushions against potential solder bridging caused by misalignment or bump diameter variations, thereby enabling fine pitch bonding with maintained reliability. The prior cushioning principle allows high interconnect density without sacrificing solder joint reliability.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Productivity

If solder mask dam is removed to achieve finer pitch, then interconnect density is improved, but electrical isolation between solder bumps and signal traces is compromised

Engineering Contradiction:
Improveinterconnect densityVSAvoidelectrical isolation
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the surface parameter of the signal trace by forming an oxide layer, which provides electrical isolation properties. This parameter change enables the removal of the solder mask dam while maintaining electrical isolation between solder bumps and signal traces. The oxidized surface acts as an insulator, resolving the contradiction between achieving fine pitch and maintaining electrical isolation.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts the electrical isolation function from the solder mask dam structure and transfers it to the oxide layer on the signal trace. This extraction allows removal of the space-consuming solder mask dam while preserving the essential electrical isolation function through the oxide barrier, thereby enabling finer pitch with maintained isolation.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables reliable and robust solder joints at finer pitches, preventing electrical shorts and allowing for higher interconnect density without increasing packaging costs, by ensuring electrical isolation through the oxide layer on signal traces.

Implementation Method 1

forming an oxide layer over the signal trace... In the event that the solder bump physically contacts the oxide layer over the signal trace, the oxide layer maintains electrical isolation between the solder bump and signal trace

Methodology Applied
Scientific EffectElectrical insulation through oxide layer: Electrical Resistance

Implementation Method 2

reflowing the solder bump to metallurgically and electrically bond to the contact pad

Methodology Applied
Scientific EffectSolder reflow metallurgical bonding: Soldering

Data Source

PatentUS7851345B2Semiconductor device and method of forming oxide layer on signal traces for electrical isolation in fine pitch bonding
Publication Date: 2010.12.14 STATS CHIPPAC MANAGEMENT PTE LTD
  • US7851345B2 patent drawing
  • US7851345B2 patent drawing
  • US7851345B2 patent drawing

AI summary

A semiconductor device has a semiconductor die with a solder bump formed on its surface. A contact pad is formed on a substrate. A signal trace is formed on the substrate. The pitch between the contact pad and signal trace is less than 150 micrometers. An electroless surface treatment is formed over the contact pad. The electroless surface treatment can include tin, ENIG, or OSP. A film layer is formed over the contact pad with an opening over the signal trace. An oxide layer is formed over the signal trace. The film layer and surface treatment prevent formation of the oxide layer over the contact pad. The film layer is removed. The solder bump is reflowed to metallurgically and electrically bond to the contact pad. In the event that the solder bump physically contacts the oxide layer, the oxide layer maintains electrical isolation between the solder bump and signal trace.