Oxide Semiconductor Layer Composition for High On-State Current
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high electrical characteristics, high on-state current, small parasitic capacitance, miniaturization, high integration, high resolution displays, low power consumption, and high operating speed, particularly due to limitations in oxide semiconductor materials.
Innovation Solution
An oxide semiconductor layer with a c-axis aligned crystalline structure is formed using indium and zinc, where the c-axis alignment proportion is higher in certain regions, and the indium content varies across different regions, utilizing atomic layer deposition and sputtering methods to enhance crystallinity and reduce impurities, thereby improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If oxide semiconductor materials are used in transistors, then leakage current is reduced, but electrical characteristics and on-state current are limited
Solution Approach 1:
The patent applies local quality by creating regions with different indium content within the oxide semiconductor layer. The first and third regions have higher indium content than the second region, creating localized variations in electrical properties. This allows different parts of the semiconductor layer to optimize for different functions: high indium regions for carrier mobility and low indium regions for stability, thereby improving overall electrical characteristics while maintaining low leakage current.
Solution Approach 2:
The patent changes the compositional parameter of indium content across different regions of the oxide semiconductor layer. By varying the indium concentration (higher in first and third regions, lower in second region), the patent optimizes electrical characteristics and on-state current while maintaining the low leakage current advantage of oxide semiconductors. This parameter variation allows simultaneous achievement of high performance and low power consumption.
2Ease of manufacture
If oxide semiconductor layer uniformity is maintained, then manufacturing is simplified, but crystallinity and electrical performance are reduced
Solution Approach 1:
The patent implements local quality by introducing controlled compositional variations in indium content across different regions of the oxide semiconductor layer. Rather than maintaining uniform composition, the patent creates specific regional differences (first region with higher In, second region with lower In, third region with higher In) that enhance crystallinity and electrical performance. This localized variation approach maintains manufacturability while significantly improving material quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in transistors with high electrical characteristics, high on-state current, reduced parasitic capacitance, and enhanced reliability, enabling miniaturization, high integration, and low power consumption, while supporting high-resolution displays and fast operating speeds.
Implementation Method 1
utilizing atomic layer deposition and sputtering methods to enhance crystallinity and reduce impurities
Implementation Method 2
utilizing atomic layer deposition and sputtering methods to enhance crystallinity and reduce impurities
Implementation Method 3
An oxide semiconductor layer with a c-axis aligned crystalline structure is formed
Data Source
AI summary
Provided are a transistor with favorable electrical characteristics, a transistor with a high on-state current, a transistor with low parasitic capacitance, or a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated. An oxide semiconductor layer included in the transistor, the semiconductor device, or the memory device includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a surface on which the oxide semiconductor layer is to be formed to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron 10 microscope, bright spots arranged in a layered manner in a direction parallel to the surface are observed in each of the first region, the second region, and the third region.