Oxide Semiconductor Layer Patterning for Uniform High-Current Transistors

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Solution Overview

Problem

Current semiconductor devices face challenges in miniaturization, high integration, high-speed operation, favorable electrical characteristics, low power consumption, and reliability, particularly in achieving small variations in transistor electrical characteristics and high on-state current.

Innovation Solution

A method of manufacturing a semiconductor device involving the formation of an oxide semiconductor with specific conductor and insulator layers, using techniques like PEALD and sputtering, to create a structure with a stacked-layer configuration of conductors and insulators that inhibit oxidation and enhance conductivity, thereby improving transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If conventional semiconductor manufacturing methods are used, then manufacturing simplicity is maintained, but device miniaturization and integration are limited

Engineering Contradiction:
Improvedevice sizeVSAvoidstructure complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The patent divides the semiconductor device into multiple distinct layers including oxide semiconductor layer, first conductor layer, second conductor layer, first insulator layer, second insulator layer, and third insulator layer. Each layer serves specific functions and enables independent optimization, allowing miniaturization while maintaining manageability through modular structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar 2D structures to 3D stacked structures by forming conductor layers and insulator layers in multiple vertical dimensions. The side surfaces of conductors are exposed and covered by insulator layers, creating a three-dimensional integrated structure that increases integration density

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If device size is reduced for miniaturization, then integration density increases, but manufacturing precision requirements increase

Engineering Contradiction:
Improvelayer formation precisionVSAvoidmanufacturing efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent forms the oxide semiconductor layer, first conductor layer, and second conductor layer sequentially before forming the insulator layers. This preliminary formation of functional layers establishes precise dimensional relationships early in the process, enabling subsequent insulator layers to be formed with controlled thicknesses that maintain manufacturing precision

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces conventional lithography and etching processes with atomic layer deposition (ALD) methods for forming insulator layers. ALD provides self-limiting chemical reactions that automatically control film thickness at the atomic level, achieving superior precision without requiring complex mechanical alignment systems

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If conventional conductor and insulator layers are used, then manufacturing simplicity is maintained, but electrical characteristics and reliability are insufficient

Engineering Contradiction:
Improveelectrical characteristic stabilityVSAvoidmaterial layer complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the material parameters by selecting specific oxide semiconductors (In-Ga-Zn-O), conductors (tantalum nitride, tungsten), and insulators (silicon nitride, silicon oxide). Each material is selected for its specific electrical, mechanical, and chemical properties that optimize device performance and reliability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures where oxide semiconductor is combined with metal nitride conductors and silicon-based insulators. These composite layers create interfaces with optimized energy band alignment and reduced defect states, improving electrical characteristics and device reliability

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach enables the creation of semiconductor devices with improved miniaturization, high integration, fast operation, low power consumption, and reliable electrical characteristics, including reduced variations in transistor performance and increased on-state current.

Implementation Method 1

utilizing silicon nitride and silicon oxide layers formed by PEALD

Methodology Applied
Scientific EffectPlasma-enhanced atomic layer deposition: Plasma Enhanced Chemical Vapour Deposition

Implementation Method 2

tantalum nitride and tungsten conductors by sputtering

Methodology Applied
Scientific EffectSputtering: Sputtering

Implementation Method 3

followed by dry etching and CMP treatment

Methodology Applied
Scientific EffectDry etching: Plasma

Data Source

PatentUS20230411500A1Manufacturing method of semiconductor device
Publication Date: 2023.12.21 SEMICON ENERGY LAB CO LTD
  • US20230411500A1 patent drawing
  • US20230411500A1 patent drawing
  • US20230411500A1 patent drawing

AI summary

To manufacture a semiconductor device by a method including the steps of: forming an oxide over a substrate, a first conductor over the oxide, and a second conductor over the first conductor; forming a first insulator to cover the oxide, the first conductor, and the second conductor; forming an opening in the first insulator to divide the second conductor into a third conductor and a fourth conductor; forming a second insulator and a third insulator to cover the oxide and the first insulator; processing the second insulator and the third insulator into a fourth insulator and a fifth insulator; processing the first conductor using the fourth insulator and the fifth insulator as a mask to divide the first conductor into a fifth conductor and a sixth conductor; and removing the fifth insulator.