Oxide Layer Thickness Control in Semiconductor Memory and IO Devices
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Solution Overview
Problem
The challenge lies in accurately controlling the thickness of oxide layers in semiconductor structures, particularly in memory devices and input/output (IO) devices, as overly thick or thin oxide layers can lead to failed program operations, leakage currents, and reliability issues due to the shared wafer formation process.
Innovation Solution
A method involving the formation of multiple oxide layers with selective removal and oxidation processes, using photomasks and photoresists to achieve precise thickness control, including forming a first oxide layer, a silicon nitride layer, trenches, and shallow trench isolation regions, followed by polishing and ion implantation to create well regions and adjust oxide layer thicknesses according to specific voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single oxide layer is formed for both memory device and IO device on the same wafer, then the manufacturing process is simplified, but the oxide layer thickness cannot be separately controlled leading to operational failures
Solution Approach 1:
The patent divides the oxide layer formation process into multiple stages: first forming a pad oxide layer across the entire wafer, then selectively removing portions in different regions, and finally forming additional oxide layers only where needed. This segmentation allows different oxide thicknesses to be achieved in memory device regions versus IO device regions, resolving the contradiction between process simplicity and thickness control precision.
Solution Approach 2:
The patent applies local quality by using photomask patterns to create region-specific oxide layer structures. Different areas of the wafer receive different treatments: memory device regions maintain thicker oxide layers while IO device regions receive thinner oxide layers. This localized differentiation enables each device type to have optimal oxide thickness for its specific operational requirements.
2Reliability
If the oxide layer is made thicker to prevent electron leakage, then reliability improves, but program and erase operations fail due to excessive thickness
Solution Approach 1:
The patent changes the oxide layer thickness parameter to different values for different device types. Memory device regions are assigned thicker oxide layers (e.g., 50-100 nm) to prevent electron leakage and ensure reliability, while IO device regions are assigned thinner oxide layers (e.g., 10-30 nm) to enable proper program and erase operations. This parameter differentiation resolves the contradiction between reliability and operational functionality.
3Ease of operation
If the oxide layer is made thinner to enable program and erase operations, then operational functionality improves, but electron leakage increases and reliability deteriorates
Solution Approach 1:
The patent segments the wafer into memory device regions and IO device regions, applying different oxide thickness specifications to each segment. IO device regions receive thinner oxide layers that enable effective program and erase operations through Fowler-Nordheim tunneling, while memory device regions maintain thicker oxide layers that prevent electron leakage and ensure data retention reliability.
Solution Approach 2:
The patent implements local quality by using photomask-defined regions to apply different oxide layer characteristics to different functional areas. IO device areas are configured with thinner oxide for operational functionality, while memory device areas maintain thicker oxide for reliability, allowing each local region to have the optimal oxide thickness for its specific operational requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the separate and accurate control of oxide layer thicknesses in memory and IO devices, enhancing the reliability of program and erase operations and ensuring proper operation voltages, thereby improving the overall performance and reducing defects.
Implementation Method 1
a program operation can be performed by pulling electrons into a gate terminal (e.g., a floating gate terminal) with the hot carrier injection (HEI) effect
Implementation Method 2
An erase operation can be performed by pulling electrons out of a gate terminal with the Fowler-Nordheim (F-N) tunneling effect
Implementation Method 3
implanting ions to form a plurality of well regions
Data Source
AI summary
A method for manufacturing a semiconductor structure includes forming a first oxide layer on a wafer; forming a silicon nitride layer on the first oxide layer; forming a plurality of trenches; filling an oxide material in the trenches to form a plurality of shallow trench isolation regions; removing the silicon nitride layer without removing the first oxide layer; using a photomask to apply a photoresist for covering a first part of the first oxide layer on a first area and exposing a second part of the first oxide layer on a second area; and removing the second part of the first oxide layer while remaining the first part of the first oxide layer.