Oxide Semiconductor LCD Pixel Structure for Low Off-Current
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Solution Overview
Problem
Existing liquid crystal display devices using amorphous silicon transistors face issues with high off-current, leading to display deterioration and high power consumption, especially in varying environmental conditions.
Innovation Solution
Utilizing an oxide semiconductor with a band gap greater than 2 eV and reduced impurity concentration to form transistors with extremely low off-current, combined with a structure that minimizes charge leakage through reduced off-current transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon transistors are used in liquid crystal display devices, then manufacturing is easier and cost is lower, but off-current is high causing display deterioration and high power consumption
Solution Approach 1:
The patent changes the material parameter from amorphous silicon to oxide semiconductor, which fundamentally alters the electrical characteristics by achieving extremely low off-current (lower than 10^-21 A) while maintaining manufacturing feasibility through sputtering deposition processes
Solution Approach 2:
The patent employs a composite structure combining oxide semiconductor layers with specific insulating materials (silicon oxide, silicon nitride) to create a transistor device that achieves both low off-current and stable display performance
2Device complexity
If amorphous silicon transistors are used in liquid crystal display devices, then device complexity is lower, but power consumption is high due to high off-current
Solution Approach 1:
The patent changes the semiconductor material parameter to oxide semiconductor with extremely low off-current characteristics, reducing power consumption during non-selection periods without adding significant device complexity
3Reliability
If oxide semiconductor with electron carrier concentration lower than 10^18/cm^3 is used, then off-current is reduced, but on-off ratio remains only 10^3
Solution Approach 1:
The patent optimizes multiple parameters simultaneously: oxide semiconductor layer thickness (50-200 nm), electron carrier concentration (10^16-10^18/cm^3), and impurity concentration to achieve both low off-current and high on-off ratio exceeding 10^8
4Adaptability or versatility
If liquid crystal display devices operate in varying environmental conditions, then adaptability is improved, but display deterioration occurs due to high off-current
Solution Approach 1:
The patent changes the transistor material to oxide semiconductor with extremely low off-current that remains stable across varying environmental conditions, preventing display deterioration while maintaining adaptability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves stable image display with low power consumption and improved viewing angle, even in varying environments, by maintaining signal voltage and reducing display deterioration.
Implementation Method 1
Utilizing an oxide semiconductor with a band gap greater than 2 eV and reduced impurity concentration to form transistors with extremely low off-current
Data Source
AI summary
A display panel for displaying an image is provided with a plurality of pixels arranged in a matrix. Each pixel includes one or more units each including a plurality of subunits. Each subunit includes a transistor in which an oxide semiconductor layer which is provided so as to overlap a gate electrode with a gate insulating layer interposed therebetween, a pixel electrode which drives liquid crystal connected to a source or a drain of the transistor, a counter electrode which is provided so as to face the pixel electrode, and a liquid crystal layer provided between the pixel electrode and the counter electrode. In the display panel, a transistor whose off current is lower than 10 zA/μm at room temperature per micrometer of the channel width and off current of the transistor at 85° C. can be lower than 100 zA/μm per micrometer in the channel width.