Oxide Liner Stress Buffer for Glass Wafer Vias
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Solution Overview
Problem
Traditional through-wafer vias in glass wafers suffer from cracking issues during fusion bonding due to the rough and jagged sidewalls of the via cavities, leading to defects and reduced reliability in aerospace and space-based applications.
Innovation Solution
A conformal deposition of a thin oxide stress buffer liner is applied to smooth the via cavity sidewalls before filling with conductive material, which reduces lateral stress and prevents cracking during high-temperature annealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-wafer vias are formed in glass wafers by direct filling of via cavities, then electrical connection is achieved, but cracking occurs during fusion bonding due to rough and jagged sidewalls
Solution Approach 1:
A stress buffer liner is deposited on the inner sidewalls and base of via cavities before filling with conductive material. This preliminary action smooths the rough and jagged sidewalls created by dicing, preventing cracking during subsequent fusion bonding while maintaining electrical connectivity.
Solution Approach 2:
The stress buffer liner acts as an intermediary layer between the rough via cavity sidewalls and the conductive fill material. This intermediate layer smooths the stress distribution and prevents direct contact between the conductive material and the jagged glass sidewalls, eliminating the cracking issue.
2Strength
If high-temperature annealing is applied to fuse glass wafers, then hermetic bonding is achieved, but thermal expansion-induced stress causes cracking at via sidewalls
Solution Approach 1:
The stress buffer liner changes the physical parameters of the via structure by providing a smooth, compliant interface that can accommodate thermal expansion stresses during high-temperature annealing. This allows the glass wafers to be fused with strong hermetic bonding without the lateral stress causing cracks at the via sidewalls.
Solution Approach 2:
The stress buffer liner serves as a cushioning layer deposited beforehand to absorb and distribute the thermal expansion-induced lateral stress during high-temperature annealing. This pre-positioned protective layer prevents stress concentration at the via sidewalls while enabling strong wafer bonding.
3Ease of manufacture
If dicing is used to create via cavities, then through-wafer vias can be formed, but rough and jagged sidewalls are created that promote cracking
Solution Approach 1:
The problematic rough and jagged sidewalls created by dicing are effectively removed or covered by depositing the stress buffer liner on the inner sidewalls and base of via cavities. This extraction of the harmful surface characteristics maintains the ease of via formation through dicing while eliminating the sidewall quality issues.
Solution Approach 2:
The stress buffer liner is applied locally to the inner sidewalls and base of via cavities, providing smooth surfaces only where needed for stress management and cracking prevention. This localized treatment maintains the overall manufacturing simplicity of dicing-based via formation while improving sidewall quality at critical locations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly enhances the resistance of glass wafers against cracking, improving yield and reliability of stacked glass wafer substrates with through-wafer vias by smoothing the sidewalls and mitigating thermal expansion-induced stress.
Implementation Method 1
depositing a stress buffer liner that conforms to inner sidewalls and a base of the via cavity
Implementation Method 2
Silica fused wafers (i.e., glass wafers) provide excellent hermetic sealing qualities when bonded together
Implementation Method 3
filling the via cavity with an electrically conductive material to form the through-wafer via
Data Source
AI summary
A through-wafer via substrate includes a substrate having an intermediate layer and a bonding layer formed on a surface of the intermediate layer. A via cavity extends through the bonding layer and into the intermediate layer, and a stress buffer liner is deposited directly on inner sidewalls and a base of the via cavity. An electrically conductive through-wafer via is disposed in the via cavity such that the stress buffer liner is interposed completely between the intermediate layer and the through-wafer via.