Oxide Liner Passivation for Tungsten Via Contact Resistance

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

As semiconductor devices miniaturize, challenges arise in reducing contact resistance in vias and outgassing from exposed middle contact etch stop layers, affecting device performance and reliability.

Innovation Solution

The implementation of an oxide liner to reduce impurities and outgassing by forming recesses in conductive features and using an oxide passivation layer to trap and remove residual impurities, promoting the transition from metastable β phase to lower resistance α phase tungsten, thereby reducing contact resistance and improving device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If via dimensions are reduced to increase device density, then device density is improved, but contact resistance increases

Engineering Contradiction:
Improvedevice densityVSAvoidcontact resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies parameter changes by modifying the physical and chemical state of tungsten through controlled oxidation and reduction processes. An oxide layer is formed on the via sidewalls, then removed to expose fresh metal surfaces, promoting the transition from high-resistance beta phase to low-resistance alpha phase tungsten. This parameter transformation resolves the contradiction by maintaining low contact resistance despite reduced via dimensions.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent explicitly utilizes phase transitions of tungsten between beta (metastable, high-resistance) and alpha (stable, low-resistance) phases. Through thermal processing and chemical treatment, the tungsten undergoes phase transformation that reduces contact resistance, enabling continued scaling of via dimensions while maintaining electrical performance.

Inventive Principle:
Principle #36Phase transitions

2Ease of manufacture

If etching processes are used to form vias, then via formation is achieved, but impurities and outgassing are introduced

Engineering Contradiction:
Improvevia formationVSAvoidimpurities and outgassing
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent converts the harmful effect of etching-induced impurities and outgassing into a beneficial process. The etching process is intentionally used to create an oxide layer on the via sidewalls, which is then selectively removed to reveal fresh, low-resistance tungsten surfaces. The harmful outgassing during etching is followed by a reduction step that removes residual oxygen and contaminants, transforming the harmful sequence into a beneficial surface preparation process.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent replaces purely mechanical/physical cleaning methods with chemical processes. Instead of relying on mechanical removal of impurities, the invention uses chemical oxidation to form controlled oxide layers and chemical reduction to remove them, providing more effective impurity removal and surface preparation that addresses the harmful effects of etching.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively decreases contact resistance and reduces outgassing, enhancing the reliability and performance of semiconductor devices by ensuring better adhesion and conductivity of conductive features.

Implementation Method 1

forming an oxide liner on a sidewall of the via to reduce impurities and outgassing by trapping impurities left behind by the etching of the via

Methodology Applied
Scientific EffectAdsorption: Adsorption

Implementation Method 2

In an embodiment, the oxide liner is formed with an O2 treatment

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 3

In an embodiment, the plasma treatment removes impurities

Methodology Applied
Scientific EffectPlasma: Plasma

Data Source

PatentUS11121025B2Layer for side wall passivation
Publication Date: 2021.09.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11121025B2 patent drawing
  • US11121025B2 patent drawing
  • US11121025B2 patent drawing

AI summary

A method of manufacturing a semiconductor device includes etching a via through a dielectric layer and an etch stop layer (ESL) to a source/drain contact, forming a recess in the top surface of the source/drain contact such that the top surface of the source/drain contact is concave, and forming an oxide liner on the sidewalls of the via. The oxide liner traps impurities left behind by the etching of the via through the dielectric layer and the ESL, wherein the etching, the forming the recess, and the forming the oxide liner are performed in a first chamber. The method further includes performing a pre-cleaning that removes the oxide liner and depositing a metal in the via.