Array Substrate Via Depth Matching for Oxide and LTPS TFTs
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Solution Overview
Problem
The fabrication processes of low temperature poly-silicon thin film transistors and oxide thin film transistors are incompatible, leading to poor process stability, long production cycles, and high costs in display devices, particularly due to differences in active layer depths and material compatibility.
Innovation Solution
A method is developed where first and second vias, and corresponding sub-grooves, are formed independently to connect source/drain electrodes to active layers of oxide and low temperature poly-silicon thin film transistors, allowing for simultaneous formation of these components in separate steps to prevent over-etching and improve etching precision without increasing process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If oxide thin film transistors and low temperature poly-silicon thin film transistors are combined in array substrates, then device functionality is improved, but process compatibility deteriorates
Solution Approach 1:
The patent divides the via formation process into two separate steps: first forming vias for oxide thin film transistors, then forming vias for low temperature poly-silicon thin film transistors. This segmentation allows each via type to be optimized independently for its specific transistor type, resolving the process compatibility issue while maintaining the ability to combine both transistor types in the same array substrate.
Solution Approach 2:
The patent performs preliminary actions by forming the oxide transistor vias first, then subsequently forming the poly-silicon transistor vias. This sequential approach allows the first set of vias to be optimized for oxide transistors without concern for affecting poly-silicon transistor performance, thereby improving ease of manufacture while maintaining device functionality.
2Reliability
If separate fabrication processes are used for oxide and low temperature poly-silicon thin film transistors, then transistor performance is improved, but production cycle lengthens
Solution Approach 1:
The patent merges the fabrication processes by combining the formation of oxide transistor vias and poly-silicon transistor vias into a single integrated process flow. Although the via formation steps are sequential, they are combined within the same manufacturing run, sharing common process equipment and materials, thereby reducing the overall production cycle compared to completely separate fabrication processes while maintaining transistor performance.
3Reliability
If via depths are increased to reach deeper active layers, then electrical connection is improved, but etching precision deteriorates
Solution Approach 1:
The patent applies local quality by optimizing via depth and etching parameters specifically for each transistor type: oxide transistor vias are formed with depths and etching conditions optimized for oxide semiconductor active layers, while poly-silicon transistor vias are formed with depths and conditions optimized for poly-silicon active layers. This localized optimization maintains etching precision while achieving reliable electrical connections for each specific application.
Data Source
AI summary
A display device is disclosed. The display device includes a display area and a wiring area. The display area is disposed with a first thin film transistor which is an oxide thin film transistor and a second thin film transistor which is a low temperature poly-silicon thin film transistor. A distance between a first active layer of the first thin film transistor and a substrate is different from a distance between a second active layer of the second thin film transistor and the substrate. The first thin film transistor includes first vias that receive a first source/drain. The second thin film transistor includes second vias that receives a second source/drain. The wiring area is provided with a groove. The groove includes a first sub-groove and a second sub-groove that are stacked, and depths of the second vias are substantially equal to a depth of the second sub-groove.