3D Oxide Semiconductor Memory Stack for Low-Power Bit-Line Switching
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Solution Overview
Problem
Current semiconductor devices using oxide semiconductors face challenges in achieving low power consumption, cost reduction, and size minimization while maintaining reliable electrical characteristics, particularly in high-temperature environments.
Innovation Solution
A semiconductor device structure incorporating multiple transistor layers with metal oxide channels, including a driver circuit and memory cells, stacked over a silicon substrate, with a switching circuit and amplifier circuit, utilizing In-Ga-Zn metal oxide for low off-state current and efficient power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple transistor layers are stacked to increase integration density, then device functionality and memory capacity are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements a three-dimensional stacked structure with multiple transistor layers (first transistor layer, second transistor layer, third transistor layer) positioned at different vertical levels. This dimensional transition from planar to vertical stacking enables higher integration density by utilizing the vertical space above the silicon substrate, allowing more functional blocks to coexist in a compact footprint while maintaining manufacturability through standardized layer replication.
Solution Approach 2:
The device is segmented into distinct functional layers: the first transistor layer contains memory cells, the second transistor layer contains switching circuits, and the third transistor layer contains amplifier circuits. Each layer is independently designed and can be manufactured using standardized processes, reducing overall device complexity while enabling high integration through vertical stacking.
2Use of energy by moving object
If metal oxide semiconductors are used to achieve low off-state current, then power consumption is reduced, but manufacturing precision and electrical characteristic control become more challenging
Solution Approach 1:
The patent utilizes metal oxide semiconductors (such as IGZO) which inherently exhibit extremely low off-state current due to their wide bandgap and unique electronic structure. By selecting materials with fundamentally different electrical parameters compared to conventional silicon semiconductors, the device achieves ultra-low power consumption while the standardized manufacturing process compensates for the increased precision requirements through material property optimization.
3Area of moving object
If transistor layers are stacked vertically to reduce device size, then area is reduced, but manufacturing precision and alignment requirements increase
Solution Approach 1:
By transitioning from planar to vertical stacking, the patent reduces the horizontal footprint of the device while accommodating multiple functional layers. The vertical arrangement of first, second, and third transistor layers allows efficient use of three-dimensional space, minimizing the device area occupied on the silicon substrate while maintaining manufacturability through standardized alignment processes.
4Reliability
If conventional silicon transistors are used in high-temperature environments, then device reliability decreases due to increased electrical characteristic variation
Solution Approach 1:
The patent employs a hybrid architecture combining conventional silicon transistors for driver circuits with metal oxide semiconductor transistors for memory and logic functions. The metal oxide semiconductor layers provide superior thermal stability and reduced electrical characteristic variation in high-temperature environments, while the silicon substrate maintains compatibility with existing CMOS manufacturing processes, creating a composite device that achieves high reliability across temperature ranges.
Data Source
AI summary
A novel semiconductor device is provided. The semiconductor device includes a driver circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The second transistor layer includes a second memory cell including a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting the selected local bit line to the amplifier circuit. The first transistor layer to the third transistor layer are provided over the silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.