3D Oxide Semiconductor Memory Stack With Switched Local Bit Lines
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Solution Overview
Problem
Current semiconductor devices using oxide semiconductors face challenges in achieving low power consumption, reduced manufacturing costs, and compact size while maintaining reliable electrical characteristics with minimal variation in transistors, especially at high temperatures.
Innovation Solution
A semiconductor device structure incorporating multiple transistor layers with metal oxide channels, including a driver circuit and memory cells, stacked over a silicon substrate, with a novel arrangement of bit lines and a global bit line for efficient data transfer and reduced parasitic capacitance, utilizing In-Ga-Zn oxide with a CAAC structure for low off-state current and high reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple transistor layers are stacked in a perpendicular direction to increase integration density, then device size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by arranging transistor layers (first transistor layer, second transistor layer, third transistor layer) in a perpendicular direction over the silicon substrate. This vertical stacking enables higher integration density while reducing the horizontal footprint of the device, effectively resolving the contradiction between device size and integration capacity.
Solution Approach 2:
The device is divided into distinct functional layers: a driver circuit layer with silicon transistors, and multiple memory cell layers with oxide semiconductor transistors. Each layer is independently structured with specific transistor types and circuit functions, allowing modular manufacturing and reducing overall manufacturing complexity despite the three-dimensional architecture.
2Use of energy by moving object
If oxide semiconductor transistors are used to achieve extremely low off-state current, then power consumption is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different transistor technologies to different functional regions: oxide semiconductor transistors are used specifically in memory cell layers where low off-state current is critical for data retention, while silicon transistors are used in the driver circuit layer where high-speed operation is prioritized. This localized application of material properties achieves low power consumption in memory regions without compromising overall device performance.
Solution Approach 2:
The device employs a composite structure combining two types of transistors: oxide semiconductor transistors (In-Ga-Zn-O) for memory cells and silicon transistors for driver circuits. This composite approach leverages the complementary strengths of each material system, achieving both low power consumption through ultra-low leakage in memory and high-speed operation in control circuits, while maintaining compatibility with existing CMOS fabrication processes.
3Productivity
If local and global bit lines are implemented for efficient data transfer, then productivity increases, but device complexity increases
Solution Approach 1:
The patent implements a hierarchical bit line architecture with local bit lines within each memory cell layer and global bit lines spanning multiple layers. This three-dimensional bit line structure enables parallel data access across stacked memory layers, significantly improving data transfer efficiency and productivity while distributing the complexity across modular functional units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a semiconductor device with extremely low off-state current, reduced power consumption, and compact size, while ensuring high reliability and small variations in electrical characteristics, even at elevated temperatures, thus addressing the limitations of existing technologies.
Implementation Method 1
a semiconductor device including a driver circuit including a plurality of transistors using a silicon substrate for a channel, and a first transistor layer to a third transistor layer each including a plurality of transistors using a metal oxide for a channel
Data Source
AI summary
A novel semiconductor device is provided. The semiconductor device includes a driver circuit and a first transistor layer to a third transistor layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The second transistor layer includes a second memory cell including a second transistor and a second capacitor. The third transistor layer includes a switching circuit and an amplifier circuit. The first transistor is electrically connected to a first local bit line. The second transistor is electrically connected to a second local bit line. The switching circuit has a function of selecting the first local bit line or the second local bit line and electrically connecting the selected local bit line to the amplifier circuit. The first transistor layer to the third transistor layer are provided over the silicon substrate. The third transistor layer is provided between the first transistor layer and the second transistor layer.